Integration provides a predictable timing closure flow for hierarchical design and test methodology
The IC design community is increasingly adopting hierarchical design methodology to cope with the growth in SoC design size and complexity, fueling the need for a manufacturing test solution that complements this hierarchical methodology, while delivering superior test quality. LogicVision's' ETLogic and ETMemory provide a patented hierarchical test and core isolation technology that enables a predictable and scaleable at-speed test methodology, facilitates effective power management during test application and provides a predictable and scaleable timing closure and ECO flow.
Hydra is an auto-interactive floor planning and hierarchical design planning solution featuring a complete physical optimization capability that enables accurate floorplan handoff. It is a standalone solution that is also fully integrated into Magma's RTL-to GDSII flow, enabling designers to manage the complexity of multimillion-gate designs to reliably achieve timing closure.
"We are very pleased that LogicVision has integrated ETLogic and ETMemory solutions with Hydra," said Kam Kittrell, general manager, design implementation business unit at Magma Design Automation. "Seamless, fully automated interoperability between design implementation and design-for-test tools significantly improves designer productivity by managing complexity of functional design logic and BIST logic in hierarchical designs."
"This integration work extends our existing interoperability with Talus Design(TM) solution from Magma," said Farhad Hayat, VP of Marketing at LogicVision. "The integration of our ETLogic and ETMemory products with Hydra will help our joint customers cope with the complexities of designing and testing of 65nm and 45nm SoCs."
The ETLogic and ETMemory integration with Hydra is in limited availability now and will be in full production in Q3, 2008.
About LogicVision Inc.
LogicVision (NASDAQ: LGVN) provides proprietary technologies for embedded test and yield learning that enable more efficient manufacturing test of complex semiconductors. LogicVision's embedded test solutions allow integrated circuit designers to embed test functionality into a semiconductor design that is used during semiconductor production test and throughout the useful life of the chip. The company's advanced Design for Test (DFT) product line, ETCreate(TM), works together with Silicon Insight(TM) applications and Yield Insight(TM) to improve profit margins by reducing device field returns and test costs, accelerating silicon bring-up times and shortening both time to market and time to yield. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com
Web site: http://www.logicvision.com/