Prolific Software Accelerates VeriSilicon's Standard Design Platform; Leading ASIC Design Firm Licenses ProGenesis to Enable Standard-Cell Layout Architectural Exploration for Wafer Foundries in China

NEWARK, Calif.—(BUSINESS WIRE)—March 22, 2006— Prolific Inc. today announced that VeriSilicon Holdings Co., Ltd. (VeriSilicon), a leading ASIC design foundry, has entered a multi-year agreement to license Prolific's ProGenesis(R) software, which accelerates the creation of standard cell libraries. VeriSilicon will use ProGenesis to do layout architectural exploration in producing multiple libraries for its Standard Design Platforms (SDP), target them to multiple fabrication processes, and produce updates as design rules change for those processes.

"With a growing list of more than 500 customers worldwide using our SDPs, ProGenesis gives us powerful capabilities for creating and customizing libraries," said Dr. Wayne Dai, president and CEO of VeriSilicon. "ProGenesis is helping our SDP take DFM, low power, low leakage, and small footprints into consideration as we explore opportunities to cover more technology processes and nodes. We have found through experience that Prolific shares our passion for outstanding design, and for providing attentive customer service."

"We are pleased that ProGenesis is helping VeriSilicon provide state-of-the-art SDP," said Dr. Paul de Dood, president and CEO of Prolific, Inc. "ProGenesis is the only tool capable of satisfying all design rules and other requirements of advanced technologies."

Complete Standard-Cell Library Control

ProGenesis is the automated cell library creation tool that reduces development time from man-weeks to days and adapts to changes in design requirements or rules. Used by independent device manufacturers (IDMs) and fabless semiconductor firms around the globe, ProGenesis supports design for manufacture (DFM) practices and design rules down to emerging 45 nm processes. ProGenesis produces standard cells as small or smaller than hand-drawn results, and can easily update cells for changing processes.

About VeriSilicon Holdings Co., Ltd.

VeriSilicon Holdings Co., Ltd. is a fabless ASIC design foundry focusing on providing semiconductor IP, front-end and back-end design services, and turnkey services including manufacturing, packaging, testing, and delivery. Over 500 customers worldwide have licensed VeriSilicon's IPs and Standard Design Platforms (SDPs), including standard cell libraries, IO cell libraries, memory compilers, optimized specifically for wafer foundries covering 90nm, 0.13 micron, 0.15 micron, 0.18 micron, 0.25 micron, and 0.35 micron process technologies. VeriSilicon is the first and only ARM certified design center (ATAP) and the first and only LSI certified ZSP design center in mainland China. For more information, visit http://www.verisilicon.com. VeriSilicon was ranked number six in Deloitte Technology Fast 500 Asia Pacific 2005 after getting No. 3 in Deloitte Technology Fast 50 China 2005.

About Prolific

Prolific Inc.'s software enables the design of today's most demanding integrated circuits, optimizing timing, power, area, and yield, while reducing overall design time and costs. Prolific's customers include companies like AMD (NYSE:AMD), Broadcom (Nasdaq:BRCM), NEC, and Samsung. Prolific is a 10-year-old, privately held, profitable company based in Silicon Valley, at 39899 Balentine Dr., Suite 380, Newark, CA 94560, telephone (510) 252-0490, fax (510) 252-0491. For more information, visit http://www.prolificinc.com/.

ProGenesis is a registered trademark of Prolific, Inc. Prolific acknowledges trademarks or registered trademarks of other organizations for their respective products and services.



Contact:
Prolific Inc.
Michael Miller, 510-252-0490

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