VHDL and Verilog test benches generated by TestBencher can optionally be linked to C++ code via the TestBuilder C++ library. TestBuilder also provides an easier method for integrating C/C++ based models into a test bench rather than using a "raw" PLI-based approach (C-based models are often used as a golden reference to compare an RTL-level model against during simulation).
TestBencher Speeds TestBuilder Development
SynaptiCAD has also ported the TestBuilder source code to Windows, making it a truly cross-platform solution. Dan Notestein, president of SynaptiCAD, said "For the first time, designers can get a complete test bench development environment for under $20K per seat that works on both Unix and Windows platforms. By combining TestBencher with the TestBuilder library, we've shattered the existing price barrier for advanced test bench verification, and at the same time created a new standard for speed and ease of use in test bench development."
TestBencher streamlines the process of creating TestBuilder-based test benches, making it easy for new users to quickly get up and running with C++ based test bench development. Traditionally C++ based test benches have required a verification engineer with significant knowledge of PLI-internals, a lot of practical experience, and a lot of patience. Using the TestBencher/TestBuilder combination, you can build a simple C++ based test bench from ground up in about twenty minutes.
TestBuilder Graphical Design Environment
TestBencher Pro can control external simulators through its graphical interface, so that compilation and simulation of the project can be handled without having to exit TestBencher. This is particularly useful for TestBuilder users because test benches are built using a C++ compiler and simulated using a VHDL or Verilog simulator. With TestBencher, all of the details about the external compiler and simulator are automatically handled, so that the test bench is seamlessly built and linked into the simulator transparently each time the user updates his test bench source files. The generated test benches can be compiled and simulated using all major VHDL and Verilog simulators. The user's C++ source files are automatically compiled with either GNU gcc or Microsoft's C++ compiler. Waveform results and log files from a simulation run are automatically imported and displayed inside TestBencher so that you develop and test your design without needing to leave the TestBencher Pro development environment.
About TestBencher Pro System Level Design
TestBencher Pro generates VHDL and Verilog test benches using graphical timing diagrams, information extracted from the model under test, and a top-level test bench file. The only code that the user writes is at the system level (the top-level test bench file); all of the other code is automatically generated. In the sequencer process of the top-level test bench file, the user specifies the order and logic in which to apply the timing diagram transaction calls to the model under test by selecting from a list of available transactions.
TestBencher Pro v8.0 is currently available on Solaris, HPUX, and Windows starting at $17,000. For more information contact SynaptiCAD at phone (800)804-7073 or (540)953-3390, email Email Contact, or web site www.syncad.com.
TestBuilder is a free open source C++ class library that extends C++ into an advanced test bench development language. For more information on TestBuilder contact Cadence at www.testbuilder.net.