MegaChips Utilizes Cadence Tensilica Xtensa Processor in Ultra-Low Power Internet of Things Sensor Hub IC

Xtensa Processor Selected After Competitive Benchmark Shows 90 Percent Lower Power Consumption for Arithmetic Operations

SAN JOSE, Calif., Feb. 9, 2015 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® Tensilica® Xtensa® processor has been designed as the core of the MegaChips frizz always-on sensor hub IC. MegaChips selected the Xtensa processor after completing a competitive benchmark that showed the Xtensa processor offered over 90 percent lower power consumption when used for pedestrian dead reckoning algorithms, which require Kalman filters.

Cadence Logo.

For more information on the Xtensa processor, visit http://www.cadence.com/news/xtensa/megachips.

frizz is a next-generation always-on sensor hub chip designed for smartphones and Internet-of-Things (IoT) wearable devices. MegaChips took advantage of the ultra-low power Xtensa processor architecture, which can perform both control and digital signal processing (DSP), customizing it for maximum throughput with three-way very long instruction word (VLIW) processing, floating point, and four-way single instruction, multiple data (SIMD) processing. By utilizing the highly flexible and automated optimization capabilities of the Xtensa processors, MegaChips was able to achieve optimum power, performance and area results for its frizz battery-operated sensor hub IC.

"We were able to take advantage of the Xtensa processor customization capabilities in this design in a short amount of time, thanks to the Tensilica automated design tools," said Kenji Nakamura, deputy general manager, AS business Headquarters at MegaChips. "No other customizable processor allows designers to integrate a four-way SIMD and VLIW for maximum throughput with 32-bit RISC control processing, which is required for best power/performance in many IoT applications. These extra capabilities can give frizz a significant advantage in the market and allow frizz to achieve the right low-power profile for wearables."

MegaChips has been an authorized Tensilica design center since 2008 and has completed many designs using Tensilica processors. The Xtensa processor can be customized to handle both performance-intensive DSP and embedded control processing functions on a single core. The patented automated Xtensa Processor Generator allows designers to create more competitive and differentiated features while achieving very low power consumption.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Tensilica, and Xtensa are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries.  All other trademarks are the property of their respective owners.

Cadence Newsroom
408-944-7039 
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/megachips-utilizes-cadence-tensilica-xtensa-processor-in-ultra-low-power-internet-of-things-sensor-hub-ic-300030440.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




Review Article Be the first to review this article
IMTS 2018 Register Now>>

Featured Video
Jobs
GIS Specialist for Metro Wastewater Reclamation District at Denver, Colorado
Upcoming Events
34th Annual Coordinate Metrology Society Conference 2018 at Grand Sierra Resort, 2500 East Second Street Meeting & Covention Center Reno NV - Jul 23 - 27, 2018
Design of Experiments (DOE) for Process Development and Validation (NTZ) 2018 at DoubleTree by Hilton San Diego Downtown 1646 Front St San Diego CA - Aug 2 - 3, 2018
FARO Measure And Inspect 2018 at Maple Hotel Bangkok Thailand - Aug 8, 2018
COMSOL Conference 2018 Bangalore at ITC Gardenia 1, Residency Road, Shanthala Nagar, Ashok Nagar, Bengaluru, Karnataka India - Aug 9 - 10, 2018
Kenesto: 30 day trial
MasterCAM



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise