DCD's I2C IP Core requires no programming

DCD’s DI2CSB IP Core is a two wire, bidirectional serial bus, which provides stable and efficient short distance data transmission between numerous devices. A very simple interface, composed with read, write and data signals, allows easy connection to target device. The DI2CSB is a technology independent design, that’s why it can be implemented in a variety of both ASIC and FPGA technologies.

May 06, 2014 -- Digital Core Design, celebrating our 15th anniversary in 2014, enhanced portfolio with a new architecture. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc., and an I2C bus. - It can work as a slave receiver or as a transmitter – says Piotr Kandora, DCD’s Member of the Board - depending on the working mode determined by the master device. A clever interface, composed with read, write and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. – The DI2CSB core incorporates all features required by the I2C specification – adds Kandora – that’s why it supports Standard, Fast, Fast Plus and High Speed transmission modes.

The DI2CSB can be easily customized in accordance to project’s needs. For instance, the DI2CSB can be found in embedded microprocessor boards, consumer and professional audio/video, home and automotive radio, low-power applications, communication systems, cost-effective reliable automotive systems etc.

More information: http://dcd.pl/ipcore/121/di2csb/ 

DI2CSB Key Features:

  • Conforms to the latest I2C specification
  • Slave operation
    + Slave transmitter
    + Slave receiver
  • Supports 3 transmission speed modes
    + Standard (up to 100 kb/s)
    + Fast (up to 400 kb/s)
    + Fast Plus (up to 1 Mb/s)
    + High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies
  • Support for reads, writes, burst reads, burst writes, and repeated start
  • 7-bit addressing
  • No programming required
  • Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready



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