Si2’s OpenPDK Coalition Releases ESD Design Flow Methodology

AUSTIN, Texas — (BUSINESS WIRE) — April 4, 2013 — The Silicon Integration Initiative (Si2) announced today that the ESD (Electro-Static Discharge) Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology “best practices” document for industry-wide adoption in order to promote a more consistent treatment of this important aspect of integrated circuit (IC) design. At advanced process nodes, it becomes increasingly critical to adhere to strict ESD design guidelines, because inadequate ESD protection can reduce effective yield and thus increase overall costs. This document provides comprehensive guidelines for incorporating ESD protection into IC design flows. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

The design of ESD (Electro-Static Discharge) protection devices in an IC should be evaluated and verified at all stages of a standard circuit design flow starting from the Cell Schematic level and ending at the Full Chip Layout level. A comprehensive set of ESD checks should be verified using appropriate tools at each of these levels to ensure that the integrated circuit has robust ESD protection. The released document describes the ESD design flow, the various checking tools that are used at each level and the requirements for each of these tools. It is available to the industry at: http://www.si2.org/openeda.si2.org/project/showfiles.php?group_id=82&release_id=558

The ESD design flow document examines such items as: Schematic Level Checking (Cell & Full Chip Level), Layout Level Checking, Power Bus Resistance Extraction Tool, Floor Planning Level Checking, Evaluation Expectations, and Tool Infrastructure.

"For technology scaling at the 130nm node and below, first-time-right product ESD protection results have become important using classical verification methodologies. The complete ESD design flow and verification as presented by the Si2 ESD Working Group starting from cell level ESD schematic design and ending at full chip layout verification is essential for the semiconductor industry to achieve successful ESD results in leading edge semiconductor technologies.” Robert Gauthier - Technical VP of Operations, ESD Association.

The goal of the OpenPDK Coalition is to define a set of open standards to define a PDK structure that will be as portable across foundries and as agnostic to EDA tools as possible. The OpenPDK from Si2 will enable greater efficiency in PDK development, verification and delivery and will provide equivalent support to all foundries, all EDA tool vendors, all IP providers, and all end users. The OpenPDK project aims to support all process nodes including high-voltage analog processes. For more information, see: http://www.si2.org/?page=1118

Membership in Si2 projects is open to all interested parties across the semiconductor supply chain. For more information see: http://www.si2.org/?page=1137

OpenPDK Member Companies

AnaGlobe Technology, Cadence Design Systems (NASDAQ: CDNS), GLOBALFOUNDRIES, IBM (NYSE: IBM), Intel (NASDAQ: INTC), Mentor Graphics (NASDAQ: MENT), NXP (NASDAQ: NXPI), Samsung Electronics (KSE: 005930), Silvaco, and STMicroelectronics (NYSE: STM).

About Si2

Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 25th year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 80 companies involved in all parts of the silicon supply chain throughout the world. See www.si2.org.



Contact:

Silicon Integration Initiative
William Bayer, 512-342-2244, ext. 304




Review Article Be the first to review this article
Rand3D

Featured Video
Jobs
Mechanical Engineer for Allen & Shariff Corporation at Pittsburgh, PA
System Designer/Engineer for Bluewater at Southfield, MI
Director of Process Engineering. for Tekni-Plex at Toledo, OH
Project Manager for Keystone Aerial Surveys at Philadelphia, PA
GIS Specialist for Fresno Irrigation District at Fresno, CA
Senior Structural Engineer for Wiss,Janney, Estner Assoicates, Inc at houston, TX
Upcoming Events
Manufacturing in America 2018 at Ford Field 1902 St. Antoine, Detroit MI - Mar 14 - 15, 2018
ACE 2018 Conference at The Westin Indianapolis 241 W Washington St Indianapolis IN - Mar 20 - 22, 2018
ESPRIT World 2018 at Indianapolis Marriott Downtown 350 West Maryland Street Indianapolis IN - Jun 11 - 15, 2018
HxGN LIVE 2018 at The Venetian Las Vegas NV - Jun 12 - 15, 2018
Kenesto: 30 day trial
Tebis
SolidCAM: SolidCAM SEE IT LIVE



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise