Capacitive effects between interconnects have become much more important lately.
They not only introduce new phenomena, such as the affecting of signals on interconnects that are closely spaced, they also increase effective capacitive loading, slowing down the speed of DSM VLSI chips.
In terms of processing, one of the limiting factors in fabricating higher and higher density chips is how closely metal interconnects can be placed together. Metal interconnects occupy a sizable percentage of the real estate on a VLSI chip. Fabrication-limited layout density is restricted by such factors as clean room classification, the type of photoresist used, the status of the etching technology, optical resolution or alternatively e-beam techniques, to name just a very few. A challenge for narrow, closely spaced interconnects is to avoid bridging that would create electrical shorts.
In terms of reliability and voltage supply, there are other limiting factors. Making the metal lines as narrow as possible, we still need to guarantee a certain current carrying capability to minimize electromigration and minimize resistive voltage drops along the metal line interconnects. This is all the more critical today, because power supply voltages are continuously reduced to minimize power consumption in VLSI chips.
Problems with both bridging and current carrying capabilities can be minimized with plasma etching, a huge step forward from classical wet-etch techniques. Plasma etching allows metal interconnects with nice, rectangular cross sections as opposed to a trapezoidal and, for narrow widths, even a triangular cross section. Then, current carrying capability is also optimized by making the metal as thick as is compatible with processing challenges such as step coverage. The other key factor for increasing current carrying capability is progress in finding the best metal composition or doping, such as with copper or other metals.
Finally, while there has been great advancements in interconnect layout density for minimizing voltage drops and maximizing reliability with large current carrying capability, they have brought with them a serious challenge for the dynamic performance of VLSI chips. The positive geometrical factors of thick, rectangular interconnects in close proximity to each other also maximize capacitive coupling between interconnects. Figure 3.7 shows such an “ideal” cross section with the associated capacitance components. For pre-DSM technologies, the capacitive component to the substrate is large but the capacitive component between interconnects is small. For DSM technologies it is, of course, the opposite. Dynamic performance parameters such as cross-talk to maintain signal integrity and excessive capacitive loading are rapidly becoming major issues.
Fig. 3.7 The Change of Interconnect Cross Sections and Parasitics
Cross-talk induces noise and noise increasingly a challenge in VLSI
chips, due to the lowering of power supply voltages with the resulting
smaller signal amplitudes that are more susceptible to noise. However,
it is not just the cross-coupling between closely spaced interconnects
that creates problems. While there is a variety of noise sources in
VLSI chips, most related to the physical layout, our discussion here is
limited exclusively to effects caused by placing interconnects closely
together. This increases capacitive coupling between interconnects and
affects signal integrity and capacitive loading. Capacitive loading
increases signal delay and power consumption. We focus on these two
effects because they can be strongly influenced by layout compaction.
These compaction steps are best performed at the back-end, after
floorplanning and place & route.
Of course, smaller signal amplitudes due to smaller power supply voltages do not mean less cross-coupling, because the degree of capacitive coupling depends on the rate of signal change and not their amplitudes. Because of the increases in speed, these rales of change also increase.
Since capacitive coupling causing cross-talk and capacitive loading between closely spaced interconnects occurs only when the voltage between these interconnects changes (like two lines switching in phase in opposite directions), there are several capacitive possibilities:
Of course, anything between these limits can occur if the signals are shifted in time against each other or if their rates of change, their rise times, differ. Because of the uncertainty of exactly what might happen, the design should take account of the worst case, such opposite polarity signals, and be based on the largest possible rate of change of signals.
In terms of cross-coupling analysis, this depends very sensitively on the exact signal shape and especially any ringing or spikes in a signal. For instance, ringing or spikes can occur for fast rise times in longer interconnects due to transmission line impedance-mismatch-induced reflections. The very successful use of the first order-distributed Elmore delay models are a good approximation for “well-behaved” signals for determining delay times and rise times. Different types of timing analyses should be used to check for noise and dynamic coupling.
We have sought to maximize the metal interconnect packing density while at the same time taking cross-coupling into account.
Again the question:
What can be done at the front-end versus the back-end?
Clearly, as previously discussed, the main leverage is at the front-end. Any back-end adjustment on a layout that has not been designed with noise sources in mind may be too little, too late. This is particularly true for noise problems, because the coupling between adjacent interconnects discussed here is only one of several possible noise sources in a VLSI chip. But again, back-end adjustments can be performed for optimization based on complete knowledge of a finished layout.
Now focusing only on interconnect coupling, increasing the thickness (height) of interconnects helps with current carrying capability and minimizing voltage drops, while the capacitance between interconnects for a given interconnect separation will increase. The challenge is as follows:
Can we lower this cross-coupling component by increasing the distance between interconnects without paying a penalty on packing density?
One approach used by the industry is to take advantage only of “empty” space. Often, metal interconnects are placed closely together on a chip when there are actually unoccupied areas surrounding the interconnects. So why not spread these interconnects within the available area without affecting the placement of any of the rest of the layout? Figure 3.8 shows an example of such spreading. On the left side is the layout before spreading, while layout after spreading is shown on the right side. Such an adjustment is not only “free” in terms of layout density, but much is gained in terms of lowering the cross-coupling, the capacitive-loading-induced additional power consumption and fabrication yield may also increase.
Of course, not all interconnects are equally susceptible to coupling. Another level of sophistication in spreading interconnects is to prioritize the interconnects that more urgently need to spread apart in comparison to others. This is also possible. We discuss the features of a tool allowing such spreading in Chapter 6.
So far, we have only minimized the degree of cross-coupling. After spreading the interconnects to the maximum, we have minimized the coupling as much as possible by modification at the back-end. Before moving to masks, we need to determine whether a VLSI chip actually works, whether the noise problems have been sufficiently eliminated. At present, tools are reaching the market that analyze at the layout level whether a VLSI chip is expected to pass the noise test.
Fig. 3.8 Lower Cross-Coupling & Higher Yield Keeping the Same Area