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A Verilog HDL Primer (Please refer to ISBN 096503917x)
Author: Bhasker, J .

Cover: Hard cover
Pages: 259
List Price: $59.95
Published by Star Galaxy Press
Date Published: 01/1997
ISBN: 0965627748


Table of Contents

Preface ..... xv
Chapter 1
Introduction ..... 21
1.1. What is Verilog HDL? ..... 21
1.2. History ..... 22
1.3. Major Capabilities ..... 22
Chapter 2
A Tutorial ..... 26
2.1. A Module ..... 26
2.2. Delays ..... 28
2.3. Describing in Dataflow Style ..... 29
2.4. Describing in Behavioral Style ..... 31
2.5. Describing in Structural Style ..... 34
2.6. Describing in Mixed-design Style ..... 36
2.7. Simulating a Design ..... 37
Chapter 3
Language Elements ..... 42
3.1. Identifiers ..... 42
3.2. Comments ..... 43
3.3. Format ..... 43
3.4. System Tasks and Functions ..... 44
3.5. Compiler Directives ..... 44
3.5.1. ''define and 'undef ..... 45
3.5.2. ''ifdef ..... 'else and 'endif ..... 45
3.5.3. ''default_nettype ..... 46
3.5.4. ''include ..... 46
3.5.5. ''resetall ..... 46
3.5.6. ''timescale ..... 46
3.5.7. ''unconnected_drive and 'nounconnected_drive ..... 48
3.5.8. ''celldefine and 'endcelldefine ..... 48
3.6. Value Set ..... 49
3.6.1. Integers ..... 49
Simple Decimal Form ..... 49
Base Format Notation ..... 50
3.6.2. Reals ..... 51
3.6.3. Strings ..... 51
3.7. Data Types ..... 52
3.7.1. Net Types ..... 52
Wire and Tri Nets ..... 53
Wor and Trior Nets ..... 54
Wand and Triand Nets ..... 55
Trireg Net ..... 55
Tri0 and Tri1 Nets ..... 56
Supply0 and Supply1 Nets ..... 56
3.7.2. Undeclared Nets ..... 56
3.7.3. Vectored and Scalared Nets ..... 57
3.7.4. Register Types ..... 57
Reg Register ..... 57
Memories ..... 58
Integer Register ..... 60
Time Register ..... 61
Real and Realtime Register ..... 61
3.8. Parameters ..... 62
Chapter 4
Expressions ..... 63
4.1. Operands ..... 63
4.1.1. Constant ..... 64
4.1.2. Parameter ..... 64
4.1.3. Net ..... 65
4.1.4. Register ..... 65
4.1.5. Bit-select ..... 66
4.1.6. Part-select ..... 66
4.1.7. Memory Element ..... 66
4.1.8. Function Call ..... 67
4.2. Operators ..... 67
4.2.1. Arithmetic Operators ..... 69
Result Size ..... 70
Unsigned and Signed ..... 70
4.2.2. Relational Operators ..... 72
4.2.3. Equality Operators ..... 72
4.2.4. Logical Operators ..... 73
4.2.5. Bit-wise Operators ..... 74
4.2.6. Reduction Operators ..... 75
4.2.7. Shift Operators ..... 76
4.2.8. Conditional Operator ..... 77
4.2.9. Concatenation and Replication ..... 77
4.3. Kinds of Expressions ..... 78
Chapter 5
Gate-level Modeling ..... 79
5.1. The Built-in Primitive Gates ..... 79
5.2. Multiple-input Gates ..... 80
5.3. Multiple-output Gates ..... 82
5.4. Tristate Gates ..... 83
5.5. Pull Gates ..... 85
5.6. Gate Delays ..... 85
5.6.1. Min:typ:max Delay Form ..... 87
5.7. Array of Instances ..... 87
5.8. Implicit Nets ..... 88
5.9. A Simple Example ..... 88
5.10. A 2-to-4 Decoder Example ..... 89
5.11. A Master-slave Flip-flop Example ..... 90
5.12. A Parity Circuit ..... 91
Chapter 6
User-Defined Primitives ..... 93
6.1. Defining a UDP ..... 93
6.2. Combinational UDP ..... 94
6.3. Sequential UDP ..... 95
6.3.1. Initializing the State Register ..... 96
6.3.2. Level-sensitive Sequential UDP ..... 96
6.3.3. Edge-triggered Sequential UDP ..... 96
6.3.4. Mixing Edge-triggered and Level-sensitive Behavior ..... 97
6.4. Another Example ..... 98
6.5. Summary of Table Entries ..... 99
Chapter 7
Dataflow Modeling ..... 100
7.1. Continuous Assignment ..... 100
7.2. An Example ..... 102
7.3. Net Declaration Assignment ..... 102
7.4. Delays ..... 103
7.5. Net Delays ..... 105
7.6. Examples ..... 106
7.6.1. Decoder ..... 106
7.6.2. Magnitude Comparator ..... 107
Chapter 8
Behavioral Modeling ..... 108
8.1. Procedural Constructs ..... 108
8.1.1. Initial Statement ..... 109
8.1.2. Always Statement ..... 111
8.1.3. In One Module ..... 113
8.2. Timing Controls ..... 114
8.2.1. Delay Control ..... 115
8.2.2. Event Control ..... 115
Edge-triggered Event Control ..... 116
Level-sensitive Event Control ..... 117
8.3. Block Statement ..... 117
8.3.1. Sequential Block ..... 118
8.3.2. Parallel Block ..... 119
8.4. Procedural Assignments ..... 122
8.4.1. Intra-statement Delay ..... 123
8.4.2. Blocking Procedural Assignment ..... 124
8.4.3. Non-blocking Procedural Assignment ..... 125
8.4.4. Continuous Assignment versus Procedural Assignment ..... 127
8.5. Conditional Statement ..... 128
8.6. Case Statement ..... 130
8.6.1. Don't-cares in Case ..... 131
8.7. Loop Statement ..... 132
8.7.1. Forever-loop Statement ..... 132
8.7.2. Repeat-loop Statement ..... 133
8.7.3. While-loop Statement ..... 133
8.7.4. For-loop Statement ..... 134
8.8. Procedural Continuous Assignment ..... 134
8.8.1. Assign - deassign ..... 135
8.8.2. Force - release ..... 136
8.9. A Handshake Example ..... 137
Chapter 9
Structural Modeling ..... 140
9.1. Module ..... 140
9.2. Ports ..... 141
9.3. Module Instantiation ..... 141
9.3.1. Unconnected Ports ..... 143
9.3.2. Different Port Lengths ..... 143
9.3.3. Module Parameter Values ..... 144
Defparam Statement ..... 144
Module Instance Parameter Value Assignment ..... 145
9.4. External Ports ..... 146
9.5. Examples ..... 149
Chapter 10
Other Topics ..... 151
10.1. Tasks ..... 151
10.1.1. Task Definition ..... 151
10.1.2. Task Calling ..... 153
10.2. Functions ..... 154
10.2.1. Function Definition ..... 154
10.2.2. Function Call ..... 155
10.3. System Tasks and Functions ..... 156
10.3.1. Display Tasks ..... 156
Display and Write Tasks ..... 156
Strobe Tasks ..... 158
Monitor Tasks ..... 158
10.3.2. File I/O Tasks ..... 159
Opening and Closing Files ..... 159
Writing out to a File ..... 160
Reading from a File ..... 160
10.3.3. Timescale Tasks ..... 161
10.3.4. Simulation Control Tasks ..... 162
10.3.5. Timing Check Tasks ..... 163
10.3.6. Simulation Time Functions ..... 165
10.3.7. Conversion Functions ..... 166
10.3.8. Probabilistic Distribution Functions ..... 166
10.4. Disable Statement ..... 167
10.5. Mixing Structure with Behavior ..... 168
10.6. Hierarchical Path Name ..... 169
10.7. Value Change Dump (VCD) File ..... 171
10.7.1. An Example ..... 173
10.7.2. Format of VCD File ..... 174
10.8. Specify Block ..... 176
10.9. Strengths ..... 179
10.9.1. Drive Strength ..... 179
10.9.2. Charge Strength ..... 180
10.10. Race Condition ..... 180
Chapter 11
Verification ..... 182
11.1. Writing a Test Bench ..... 182
11.2. Waveform Generation ..... 183
11.2.1. A Sequence of Values ..... 183
11.2.2. Repetitive Patterns ..... 185
11.3. Testbench Examples ..... 190
11.3.1. A Decoder ..... 190
11.3.2. A Flip-flop ..... 191
11.4. Reading Vectors from a Text File ..... 193
11.5. Writing Vectors to a Text File ..... 195
11.6. Some More Examples ..... 196
11.6.1. A Clock Divider ..... 196
11.6.2. A Factorial Design ..... 198
11.6.3. A Sequence Detector ..... 201
Chapter 12
Modeling Examples ..... 204
12.1. Modeling Simple Elements ..... 204
12.2. Different Styles of Modeling ..... 208
12.3. Modeling Delays ..... 210
12.4. Modeling Conditional Operations ..... 212
12.5. Modeling Synchronous Logic ..... 213
12.6. A Generic Shift Register ..... 217
12.7. State Machine Modeling ..... 218
12.8. Interacting State Machines ..... 220
12.9. Modeling a Moore FSM ..... 224
12.10. Modeling a Mealy FSM ..... 226
12.11. A Simplified Blackjack Program ..... 228
Appendix A
Syntax Reference ..... 232
A.1. Keywords ..... 232
A.2. Syntax Conventions ..... 233
A.3. The Syntax ..... 234
Bibliography ..... 251
Index ..... 253