# Logic Design for Array-Based Circuits

### by Donnamaie E. White

Copyright © 1996, 2001, 2002 Donnamaie E. White

## Symbols

fmax
Maximum clock frequency; highest rate at which a clock input can be driven and still maintain stable transitions.

ICC
The current drawn by the macro, into the VCC supply pin of the circuit. For individual macros, the current drawn by that macro (TYPICAL). When computing the supply current for an array, it will be a function of the macros used in the array plus the overhead current for the I/O mode. It may also be a function of the number of TTL input macros.

ICC HIGH
The current drawn by the macro when the output is logical HIGH.

ICC HIGH-Z
The current drawn by the macro when the output of high-impedance OFF.

ICC LOW
The current drawn by the macro when the output is logical LOW.

IEE
The current drawn by the macro, into the VEE supply of the circuit. For individual macros, the current drawn by that macro (TYPICAL). When computing the supply current for an array, it will be a function of the macros used in the array plus the overhead current for the I/O mode.

II
Input HIGH current at maximum Vin.

IIL
TTL input current when the input logic level is LOW.

IIH
TTL input current when the input logic level is HIGH.

IOH
TTL output current when the output logic level is HIGH.

IOL
TTL output current when the output logic level is LOW. The current drawn by the macro is the sink capability of an output. For AMCC bipolar Logic Arrays this is 20 mA.

IOS
Output short circuit current.

PW
Pulse width. The minimum time required between edges of the driving signal. AMCC specifies PW as the worst-case (the minimum for which operation is guaranteed).

Th
Hold time; the minimum time between the application of an active edge of the clock signal and the removal of the data signal being clocked. A negative hold time implies that the data may be removed before the arrival of the active edge of the clocking signal.

TJ
Junction temperature of a device; specified as the maximum for which operation can be guaranteed. For MILITARY circuits, TJ = 150o C. For COMMERCIAL circuits, TJ = 130o C.

TPHL
Propagation delay time, HIGH-to-LOW-level output.

TPHZ
Output disable time, HIGH-to-high-impedance (off) output.

TPLH
Propagation delay time, LOW-to-HIGH-level output.

TPLZ
Output disable time, LOW-to-high-impedance (off) output.

TPZL
Output enable time, high-impedance (off) to LOW output.

TPZH
Output enable time, high-impedance (off) to HIGH output.

Trec
Recovery time; the minimum time required between the removal of a set or reset and the next active edge of the clock for the correct operation of the device to be guaranteed.

Tsu
Set-up time; the minimum time between the application of a data signal and the active edge of the clock. A negative set-up time implies that the data must remain "set-up" after the active edge of the clock. AMCC specifies Tsu as worst-case (the minimum for which operation is guaranteed).

VIH
High-level input voltage. The minimum voltage that should be applied to the input of a device for a logical 1 voltage level. A maximum may be specified; the input current will become very large if this maximum is exceeded.

VIK
Input clamp diode voltage, limits input swing below ground (TTL).

VIL
Low-level input voltage. The maximum voltage that should be applied to the input of the device for a logical 0 voltage level.

VOH
High-level output voltage.

VOL
Low-level output voltage.

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact dew@Donnamaie.com