Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Last Edit July 22, 2001
Power Reduction Techniques
Regardless of the array technology, items whose use will increase the power dissipated by the array should be carefully chosen. A tradeoff or balance of different design objectives should reflect judicious selections that maintain speed while keeping power dissipation to a minimum and circuit size within the array constraints. Power considerations are no less serious for the large CMOS and BiCMOS arrays.
Table 7-8 summarizes the design choices that contribute to higher power; which choices are possible depends on the array series.
Table 7-8 Power Dissipation Contributors
Table 7-9 summarizes the choices that can be made to reduce power and the design tradeoffs that these may require.
Table 7-9 Low Power Options