Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Timing Analysis for Arrays
Last Edit July 22, 2001
Example Equations for Extrinsic Loading - Output Nets
ECL and TTL output macros are often specified with no capacitive loading on the macros. One method for manual computation of the effect of output pin capacitive load on the propagation path is:
The AMCC MacroMatrix AMCCANN user interface on the workstation allows the specification of the package, the package pin capacitance and the system load. Both package pin and system load capacitance may be specified as default values (all pins identical) or on an individual pin or group of pins basis. The output loading delay is automatically computed and added to the annotation files. All simulations are performed with annotation delay files.
Output net k-Factors are shown in Table 5-4 for the Q5000 Series. These are typical vales and must be adjusted to worst-case. Refer to Table 5-3b for the output values for the Q20000 Series for comparison.
Table 5-4 Example Output K-Factors kcap
Package pin capacitance varies from 1pF to 18pF on larger packages (specific pins). The variance on a single package can be as wide. System loads are by default TTL = 15pF and ECL = 5pF. Loads that exceed 30pF can be seen to begin to affect the timing in a significant way.
A 50pF load represents 3.6ns delay when driven by a TTL output. For the library from which these were taken, macro delays are in the 1-2ns range.
The output load could swamp the rest of the path, offsetting any design optimization that was performed without considering the load to be driven.
These example k-factors are typical, which means that the delay must be multiplied by a worst-case multiplier to find the worst-case maximum delay. For the library chosen (AMCC's Q20000), this is 1.45 for Military, or a 50pF load on TTL is 5.22ns maximum worst-case MIL
Also, note the ECL skew - rising edges are slower. This may offset macros whose intrinsic delays are the reverse (rising edge propagates faster). Path skew is discussed later.
Note: When computing tester limits for path delay evaluation during AC test, the system load is replaced by the tester load for the pin. Tester loading is related to the output macro type. The package pin capacitance would remain the same. The use of tester inaccuracy adjustments such as an added load of 0.15 pF is array and vendor specific.
Q5000 Example (Front-Annotation)
If a Q5000T internal S-option macro has an unloaded propagation delay (Tpd) of 0.65 ns, is wire-ORed with two other S-option sources (WIREOR3), and fans out to six loads, each with a fan-in of 1, compute the worst-case maximum delay through the loaded macro. Assume a Military-grade circuit.