What: Designing Low-power SoCs for Multimedia and Baseband
When: October 14, 2009 @ 8 am Pacific / 11 am Eastern
Where:
http://seminar2.techonline.com/registration/distrib.cgi?s=1425&d=2889
How: Live over the Internet -- Simply log on to the web at the
address above.
Contact: Richard Kingston, 408 807 9620
This CEVA webinar will deliver a fresh perspective on the main challenges involved with designing advanced SoCs while maintaining low-power. It will provide insights into how SoC architects and designers can build state-of-the art SoCs for low power using different techniques and processor architectures.
Topics to be covered:
-- Future challenges in low power SoC design
-- Key concepts in building an advanced processor architecture for low
power
-- Current trends and techniques used in low power processor architectures
-- Implementation and verification flow of processors designed to meet low
power
Who should attend:
The session should be attended by SoC architects, designers and system engineers who plan to implement SoCs with strict power constrains such as chips targeting battery powered devices.
Speakers:
-- Ran Snir - VLSI Department Manager, CEVA
-- Eyal Bergman - Director of Product Marketing, CEVA
If you are unable to participate during the live webcast, the event will be archived at http://seminar2.techonline.com/registration/distrib.cgi?s=1425&d=2889.
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is a leading licensor of silicon intellectual property (SIP) DSP Cores and platform solutions for the mobile handset, portable and consumer electronics markets. CEVA's IP portfolio includes comprehensive solutions for multimedia, audio, voice over packet (VoP), Bluetooth and Serial ATA (SATA), and a wide range of programmable DSP cores and subsystems with different price/performance metrics serving multiple markets. In 2008, CEVA's IP was shipped in over 300 million devices. For more information, visit www.ceva-dsp.com.
SOURCE CEVA, Inc.
Web site: http://www.ceva-dsp.com/