MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—February 21, 2007— Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced JasperGold(R) Verification System v4.3, a new release of the company's flagship formal verification solution that delivers major advances in performance, property modeling and ease-of-use. New in version 4.3, Jasper introduces InFormal(TM) Design Analyst, a first-of-its-kind formal verification solution targeted to address designer 'sandbox' verification without requiring the development of properties or a testbench for simulation. JasperGold System v4.3 also includes a new parallel engine multi-processing architecture that maximizes verification performance. Also new in release 4.3 is the delivery of industry-leading formal support for SystemVerilog local variables which provide users with an efficient way to handle complex data and design constructs. Both novice and advanced users of formal verification, as well as design engineers with no formal experience, will benefit from the performance, ease-of-use, modeling, and design analysis features of JasperGold Verification System 4.3.

"JasperGold System 4.3 is a landmark release for the formal industry. Not only does it improve performance and usability for verification engineers, but it also introduces the first formal solution addressing the 'sandbox' verification needs of design engineers. JasperGold's industry-leading implementation of SVA local variables also opens new applications for transaction-level formal verification," said Craig Cochran, vice president of marketing at Jasper Design Automation. "Several major companies have broadly deployed JasperGold Verification System, and with the market adoption rate of full formal verification accelerating, JasperGold System v4.3 delivers the capabilities needed to speed broad deployment of formal verification on large projects."

Parallel Engine Multi-threaded Processing Delivers Higher Performance

JasperGold Verification System v4.3 includes a new parallel engine multi-processing architecture, enabling users with fast or multi-core machines to benefit from increased verification performance, as well as an easier usage model. With parallel engine multi-processing, JasperGold System v4.3 launches multiple proof engines, with differing, complementary strengths, on each property to be verified. The first engine to complete a proof then terminates the other engines and the process moves to other properties. This new architecture also simplifies engine selection, since the fastest engine always wins.

Formal Verification of SystemVerilog Local Variables

JasperGold System v4.3 also includes industry-leading support for formal verification of SVA local variables. SVA allows variables to be defined locally within sequences and properties. These local variables are then used to maintain state within the pipeline of events described by the sequence. Local variables are particularly useful for capturing and comparing transaction flow through the pipeline, and provide SystemVerilog users with powerful modeling capabilities that can enable transaction-level formal verification.

Introducing InFormal(TM) Design Analyst

JasperGold System v4.3 introduces InFormal Design Analyst, a new application for formal verification targeted to address the 'sandbox' verification performed by design engineers. Without requiring any properties or testbench, InFormal Design Analyst enables a design engineer to statically demonstrate the behavior of a design by manipulating automatically generated waveforms. This new application of formal verification reduces design engineers' dependence on simulation and testbenches for 'sandbox' verification, and requires no property development or experience with formal verification tools.

Pricing and Availability

JasperGold Verification System v4.3 is currently available. The new Parallel Engine Multi-processing Option to JasperGold Verification System is priced at $25,000 for a one-year floating time-based license.

See JasperGold Verification System 4.3 at DVCon

To learn more about JasperGold Verification System v4.3, or to view a demo, please visit Jasper in booth #201 at the Design and Verification Conference and Exhibition (DVCon), at the Doubletree Hotel in San Jose, California, February 21-22, 2007.

About Jasper Design Automation

Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company's flagship product, JasperGold Verification System, is the first verification product to deliver complete "deep formal" systematic verification, ensuring correctness where it matters most. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold Express, Jasper's formal ABV solution, provides the industry's leading "light formal" solution, complementing simulation-based approaches by accelerating bug hunting as well as coverage attainment. The JasperGold family quickly isolates bugs with a fast, static debugging capability, and then proves the absence of bugs, trimming design schedules. For further details on how to ensure guaranteed correctness where it matters most, please visit http://www.jasper-da.com.

Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan and InFormal are trademarks or registered trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

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