By Monday, the 6th, as Bavaria successfully dug out from under the heaviest snowfall in years, DATE got underway - offering attendees its usual warmth, hospitality, and excellent opportunities to learn both at a personal and a technical level. Unfortunately, those still enroute to Munich faced further delays or cancelled flights due to the weather, their troubles compounded by transportation strikes in various locales across Europe. Eventually most arrived (approximately 5000 people attended), and were glad they had persevered in order to attend DATE and participate in the conference, to see and be seen amidst the assembled design community there.
At a technical level, the conference was rich in content. General Chair Georges Gielen, Professor at the Katholieke Universiteit Leuven, told me the program committee received more paper submissions this year than ever before, just short of 900, and that DATE has come to be respected worldwide for the quality of its technical program.
Looking through the conference offerings - which ranged from design for manufacturing (DFM), networks on chip (NoCs), wireless sensor networks (a particular favorite of the Europeans), embedded systems, reconfigurable computing, and automotive electronics, to timing and noise analysis, on-chip power and leakage reduction, design verification, defect modeling, and nanotechnology, to mention a few - Georges Gielen and his committee, including Program Chair Donatella Sciuto, Professor at the Politecnico di Milano, could be justly proud of the depth and breadth of the DATE 2006 program.
It was not possible to attend everything - in fact, a number of attendees lamented that they could not be at more than one session at a time, and ended up having to choose between multiple, simultaneous offerings that all promised excellent content. This is not a problem unique to DATE, but a problem always associated with a conference of this size. Many highly informative sessions must run concurrently to present everything within 3 or 4 days. What follows are only a few of the highlights of my days at DATE 2006:
** The keynote address delivered on Tuesday morning at DATE by Dr. Wally Rhines, Chairman and CEO at Mentor Graphics and Chair of the EDA Consortium (EDAC) was nothing short of a magnus opus. Rhines simply said it all - simply.
With the best slides I've ever seen, Rhines laid out the reality of the EDA landscape today - the types of companies, the economics of large companies versus small, the financial and technical impact of the innovation/acquisition cycle within EDA, how capital flows in and about the EDA ecosystem, how the tools are purchased and incorporated into the design flow, how the distribution of design starts between gate arrays, cell-based ICs, ASSPs, and FPGAs has varied over the last decade, and how the process technologies have evolved over the last 15 years.
Then, he illustrated the CAD tool purchase-and-use ecosystem structure within a company, and how the tensions are arrayed between software and hardware designers, system architects and chip designers, analog and digital designers, and designers and manufacturers. (see Saving the Best for Last below.) That complete, he graphically illustrated how EDA bridges all of these paradigms and eases the tensions therein. Now that last may have been more about the idealized EDA than the gritty reality, but the clarity of Rhines' presentation excused what might have been perceived as a simplification.
His keynote was simply great, and how do I know? Every single subsequent conversation that I heard at DATE referenced back to Rhines' talk on Tuesday morning. It was that simple, and it could not have been a better intro to everything that followed at DATE, particularly if you're interested in EDA.
** Tuesday morning, after the opening ceremonies and keynotes, Dataquest's Gary Smith moderated a panel that addressed "economic and strategic decision making for system design." Panelists included executives from Toshiba, Actel, Cisco, Tensilica, MathWorks, and Cadence. The group had some pretty snappy slides, and worked together well to provide a nice overview of the situation in ESL.
Toshiba's Armin Derpmanns summarized what is perhaps the single biggest issue facing the semiconductor industry today: "How do I incorporate all of the manufacturing and yield issues back up into my design work?" That may sound like a question that belonged on a design for manufacturing panel, but it actually fit well on the ESL panel, as well.
Actel's Dennis Kish enumerated other issues that add to the challenges: time-to-market pressures which abbreviate product-development time, constantly evolving standards which are difficult to track and implement, market demands for additional, sophisticated end-product features, consumer-driven pricing pressures, and the complexities of global suppliers and markets.
Tensilica's Chris Rowen, not surprisingly, said that multi-processor chips can help address these problems, plus alleviate some of the on-chip power problems facing designers today.
Cisco's Massimo Prati said additional solutions of "incredible elegance" include the use of advanced substrates, SIPs, and system-level-centric design philosophies - the actual point of the panel.
MathWork's Jim Tung - Gary Smith called MathWorks one of the hottest companies at the conference - said system-level design offers a plethora of advantages: opportunities for innovation, lowered project risk, better designer productivity, reduced development costs, shorter time to market, better team communication, and increased IP reuse. Gray Smith, the ultimate system-level design evangelist, beamed.
Finally, Cadence's Ted Vucurevich posed the uber-question: "Is semiconductor design improved by ESL?" Ted concluded that the answer is yes, particularly if system-level design is interpreted as platform-based design, with a dollop of model-based design thrown in for good measure.
In addition: Lunch at DATE is an amazingly delicious affair - good food and a choice of red or white wines served up to hundreds of people efficiently and graciously. Unfortunately, Gary Smith and I couldn't locate our meal tickets on Tuesday, and had to scramble to get sustenance with the help of some nice people at the registration desk. Gary ended up with little time to eat in the few minutes that fell between the end of his late morning panel and the start of his early afternoon event. I think if Gary's going to be asked to do 4 panels on a single day, somebody needs to make sure his meal is delivered to him personally - he shouldn't have to go looking.
** On Tuesday afternoon late in the day, competing for audience with the Executive track panel on DFM that included Synopsys CEO Dr. Aart de Geus, and Happy Hour out on the Exhibition Hall floor itself, I moderated a panel in the Exhibition Theater. The topic of the hour was how to balance design trade-offs between project specifications for power, performance, and programmability - the concept of 3D Design. LSI Logic's Mike Casey, CriticalBlue's David Stewart, CoWare's Johannes Stahl, and Ignios' Mark Lippett were the panelists.
As the discussion between the panelists unfolded, additional 'P' words were added to the list, above and beyond Power, Performance and Programmability. They included Platforms, Parallelism, Processors, Partitioning (between the hardware and software portions of a design), Prototyping, Prima Donnas (that would be both analog and digital designers), Pragmatic (reaching realistic design solutions within rational development schedules), Persuasion (important across inter-disciplinary teams), Price (always a concern), and Pain Point (that moment when new tools and/or methodologies are embraced).