Ponte Solutions - Design for Yield (DFY)
[ Back ]   [ More News ]   [ Home ]
Ponte Solutions - Design for Yield (DFY)


In order to establish differentiation or to tout a significant strength of a company or a product line marketeers create new terminology or acronym such as DFT for Design for Test (or Testability) or DFM for Design for Manufacture (or Manufacturability). There are so many terms that one can speak of Design for “ilities”. Of course every design team is concerned with these metrics but a given design tool might be especially well suited to improve a design in these areas. A relatively new term is DFY for Design for Yield. DFY might be considered a subset of DFM or a new generation of DFM. Ponte Solutions is a startup firm in this DFY space. I had an opportunity to interview Jerry Rau who has recently joined Ponte as VP of Worldwide Sales.

Would you give us a bit on our background?
My background is a combination of semiconductor and EDA, a variety of different positions. My background is actually chemical engineering from MIT a long time ago. My first job was working in a fab which turns out to be relevant to my new position. When I was in the fab, I got interested in the business side and moved into marketing. From there I went to LSI Logic. While I was there I got a masters degree from Stanford in Material Science, semiconductor physics kind of stuff. I went to LSI Logic as a project manager. I was there a few years learning about the ASIC model. Then I went to Synopsys as product manager for version 1.2, so quite early there. I had a lot of different jobs at Synopsys. Went into business development and ultimately into sales. I came back around to get back into a smaller company, Ponte Solutions, and sort of put it all together into a role in a software company where most of the people around me have a background in semiconductor as well. Our mission is to bridge the physical world of what's going on in the fab in terms of defects and yield loss into the design side.

On Ponte's website your biography states “As IP & Professional Services Sales Director at Synopsys, Rau's leadership addressed significant IP license issues faced in the emerging China market.” What were those issues and how did you address them?
As you know China has a less than robust IP protection environment. While I was at Synopsys, one of my jobs was managing a sales team selling IP and professional services for Synopsys' products in the Asian market, in particular China. We had sort of a conflict. We wanted our product to be sold in the fastest growing market in the world but at the same time you are sort of (I am not sure of the right phrase) feeding the tiger. You are selling IP, you sell it once. If it's misused, it could undermine all future sales efforts. We had a great hesitation about putting out our very valuable IP into the China market. We addressed it in two ways. First, we did security audits of global thinking companies in China (I won't name them). The very biggest companies in China are trying very hard to overcome whatever bad image the China market has for IP protection. They are actually protecting IP probably better than anyone else in the world. We really dug into what they are doing to understand whether we could trust that environment or not. The second thing we did was the IP we were selling in most parts of the world was at the RTL level which is highly transportable. We looked at how we could harden the IP in a manner that when it was delivered into China, if it got out, it would do much less damage but it would be still useful to complete the design phase.

Again your biography says you managed third party sales channels. Mostly in Asia?
Yes, mostly in Asia. I took that job when Synopsys acquired Avanti. We suddenly acquired all the third party channels that Avanti had. They had many more than Synopsys at the time, mainly throughout Asia. As part of that acquisition and building out the sales channel, we decided to keep some of those on board although there were a few scattered throughout the other channels.

It is not unusual for a company to have overseas partners who understand the local culture, language and business processes. But these partners can be hard to control and may not have sufficient focused resources.
Coming from Synopsys you could make them focus, if you wanted to, because you have enough product line that they can dedicate resources or you can say this overlaps with our direct sales force and we would like to find a way to transition it in. Distribution from the perspective of a Synopsys is very different than that of small company.

What attracted you to move from Synopsys, an industry leader, to a small company like Ponte Solutions?
When I joined Synopsys, it was a small company. I was number 100 or so. It was a small company that had a great product that customers were clamoring for. I got to be part of some fantastic growth. Honestly throughout my career I was always saying to myself that I am a startup kind of guy, a guy who wants to create things. But the ride was too much fun at Synopsys, doing great things and growing to over a $1 billion. What really attracted me to Ponte is that when you talk to a customer about what Ponte does and the whole design for yield type of market, the return on investment and the need is just absolutely apparent. In so much of EDA you get into these conversations about saving engineering man-days and time to market. Everyone puts up the same slides, waves the flag around that without a whole lot of differentiation. When I am visiting customers from the Ponte side absolutely everybody rallies to that and says “Wow, if you could save us 1% on yield or help us reduce the die size without killing the yield that goes directly to cost savings and to the bottom line.” Finally I saw a company that looks like it could really make a difference in the business model of our customers. It was too exciting to pass up.

Would you give me an overview of Ponte Solutions?
The company was started about 3 years ago. I wasn't here at the time so I don't have all the details about what the motivation was. What we are focused on is what I would call third generation DFM or DFY (design for yield). It is very customer driven. The first generation of DFM was companies like TDS that are really helping companies define the process control window. That's completely on the fab side that says that the window on this edge is from A to B and as long as you are in that window we expect the transistors to function and the metal won't evaporate and so on. The second generation of DFM is what I would call optical enhancement of the GDS. Make a mask so that when you shine light through it, it won't degrade. This is commonly called RET for resolution enhancement techniques. You are probably familiar with a lot of companies doing that. That's a fairly big market and a valuable one. A lot of investment is going there. The third generation is what we are doing which is to take the failures that happen on the manufacturing side and capture them in a way that designers can do something about that, to anticipate that if I design this way my yield will suffer or if I design it this way, my yield may be better and drive my yield numbers up from the design side not just from the standpoint of can I get the process operating within this window.

The company began life as E-Z-CAD. Why did the company change its name to Ponte Solutions?
I think E-Z-CAD doesn't really describe what the company does. It doesn't help build a brand. It doesn't help people understand what it does. Ponte on the other hand is nice, it's easy to remember. It actually means bridge in Italian. That's what we are doing - building a bridge from manufacturing to design. So it sort of makes sense. It's a very nice name, short, and memorable. When it is dissected it has some relevance to this market.

Looking at the logo I can see something that looks like a bridge.
I think Alex and others that started the company and were in stealth mode, wanted to come up with something quickly that did not give anything away; a moment of engineering mischievousness. Let's just call it EZ Cad and see where it goes form here.

How many employees does Ponte have?
About 70 now! Probably 10 to 15 are in the US. The bulk of them are in engineering in Armenia. It turns out to be a fantastic place to have a R&D team because first of all it has a cost structure that is less expensive than the US and second of all it is a very talented team. There are a whole lot of mathematician and software developers that have come out of Armenia and the former Soviet Union. I would characterize the people that I have met from Armenia who work for Ponte as extremely hard working, dedicated, motivated every bit as much as anyone I have met form India or China. It is a pretty good situation there.

Would you comment on the number of customers and revenue that Ponte has?
I don't think I can announce what those numbers are. We do have revenue. We are shipping product that customers pay for. We are in a production mode. We have a set of customers using the product, the first versions of releases. We haven't officially announced the product, we have announced the company but the product announcement will come up in the next couple of months. At that time we will give some details about how people are using it and what impact it has had.

Your web site does not have a description of the product.
I will tell you in essence where we're headed which is developing a yield model. Usually the way yield has been handled on the design side is through design rules. The issue there is that the fab has simply said that if you follow these rules, the design will yield. We all know that this is breaking down. Yields are not high at 90 nm and below. The solution to that is to provide a model instead of rules that provides the tradeoffs. If you can afford to do this, maybe spreading things out a little bit more, you should be able to get more yield, maybe doubling up on vias. There is a whole set of techniques there. We are trying to capture that in a model that will cover a wide variety of different kinds of defects. That way with our first tools and analysis design teams can look at the design and make some quantitative judgments the yieldability of their design work.

The rule based approach to DFM is dependent upon process node, the fab and so forth. Are you models also dependent on these factors or are their generic?
The models are generic because it is physics. But to make them really work, you need foundry data. One of the things we haven't announced the particulars about is that we have cracked the foundry model. There will be foundry data available for use with our tools. Our customers have told us that this is a requirement. They have helped us working with the foundries to make that data available. That's actually one of the big barriers that you hear when you talk to small companies that are in this space. You are going to find that having the foundry data is a critical element to the believability of the analysis. In general the foundries don't want to give out their defect data because they will essentially admit that they have failures. Everyone knows that they have failures but they don't want to publish that data. We have come at them from the standpoint that the customers want it because they need to be able to predict what their costs are going to be and we've also built a model around it where there is encryption. So the actual data is protected.

Are there any competitors coming at the problem in a similar way?
Not that we are aware of. There are a lot of companies that are focused on what I would characterize as second generation. I am not aware of any companies focusing where we are on being the design side, building this statistical yield model.

What is your sales model, direct or indirect?
A combination! We have already signed up two distributors. We will probably make some public announcements about that but it is not a secret. A group in Taiwan called Markettech (MIS) and a group in Korea called Win Technology. We use a combination of direct and distributors.

What is the packing of the product (development license, royalty, …)?
At this point we are not going to reinvent the wheel. We are going to go with a straightforward EDA software license, primarily subscription. A small portion of customers have asked us for perpetual license which we will have as well. As a small company we are not going to attempt to change the market to some different formulation.

What is the price range for the product?
It will be in the $100K range to get started. The product announcement will have more specifics in a couple of months.

Would every design engineer have a seat or only certain experts?
The way I characterize it, it is really at the physical design level not at the RTL level, not at the ESL level. It could be used as early as someone is doing floorplanning. It can be used in library development and used at the system design level to make tradeoffs. These are the three areas that are most likely to use it.

How does DFY relate to DFM? Subset? Complement?
We touched on that earlier in terms of the three generation and how the third generation is actually DFY. My belief is that DFM is one of those terms that has become somewhat meaningless because what does it mean to design in order to be able to manufacture. If you are not designing it to be manufactured, what is the point of designing it. The issue is more one of cost and bridging from the manufacturing data into the design side. The first two generations are purely on the manufacturing side. A designer doesn't need to know what the mask actually looks like that is going to print his circuit. A designer doesn't really need to know where the process windows are on exposure, aperture and so forth. They just assume that if I follow a set of rules, I should get yield out the back end. DFY is that third generation where a designer can get data in a model in a manner that is meaningful to make tradeoffs that impact yield. Manufacturability is not a binary where it works or it doesn't. It is a statistical event that happens.

Armed with this data what steps can a designer take to increase the yield of his design?
It's a little beyond our tools. Out tools are analysis tools. For instance, we can look at different floorplans of a chip that are all possible at trial layout and then run an analysis to see which one more likely to have less yield loss, i.e. will yield better. You can also look at library elements, different figures of merit on different ways of laying out a cell and which one would be yielding well. One of our early customers looked at the library elements of a very large chip. They determined that something like a dozen library elements were each used 50,000 times. There were some yield issues within those elements. By going back and resigning those elements without a penalty in area they were able to increaser the yieldability of that overall chip. The analysis is to find the issue, figure out something to do with it and give yourself a benchmark of whether you can improve or not. It could be at the floorplanning level, the aspect ratio of the chip, or it could be down to a cell level. It could be a library element.

Does Ponte have any patents on their technology?
We are working on patents. We have submitted some.

Is this product for general usage or are there some applications that would benefit most?
We haven't found that yet. At this point we are being approached by companies in different industries with different applications. It doesn't appear that there is any particular niche. There is certainly no limit to applying this product to different kinds of applications. The question I think you are asking is “Are there certain applications crying out more than others?” I haven't seen a pattern yet.

Does the need for and the value of your product increase as one goes from 130 nm to 90 nm to 65 nm?
Absolutely! I've heard that going to 90 nm yields are really going down. I've heard estimates at 65 nm getting single digit yields. There's a lot of room to improve there. The design rules really exploded The foundries don't really have a great grip on following those rules because it has been hard and fast rules like keeping your metal this far apart that have become traditional rules. If there's a second structure that is in the vicinity of the metal, use a different rule. It's becoming too much to manage for the people who have to actually implement those rules.

Prospects recognize the problem and see the value in what you offer. How do you convince them that you can deliver?
The first thing you need is vision match. The operative question is “If you yield could improve by a small amount, would that be a good thing?” The calculation goes” How big is my wafer? How many dies? What's my current yield? What does that translate into in terms of cost savings by running less wafers or perhaps it is from the standpoint of now I get more good dies through the fab early on, actual have product on the shelf. Right now as an example I think Microsoft wishes that they could have made more Xbox but the yields have been pretty dismal is my understanding. The benefits could be spoken of in a number of different ways. I mentioned before if you have this conversation everybody is in favor of having a higher yield or lower cost die. When you talk to people about ESL I think the reaction is some people say “That's exactly where we want to be.” Other people say “That's kind of interesting but why would I use that or that's a little too domain specific. We are a little different. It doesn't apply.”

In reality anybody who is making a chip whether they are a chip company, a foundry, an IP company have an interest in making the yields as bets as they can be.

How do you convince prospect (reference, benchmarks, ..)?
All of our customers are running benchmarks, seeing what the differences are in comparison. In test cases it's apparent to them. I will give you an example. Improving yield is not a new thing. There has always been a first spin of silicon. Now let's do a second spin maybe change this functionality and by the way clean up a few things to make the yield higher. One company we are engaged with had spent six months doing a diagnosis on why a chip was yielding so poorly. We engaged them and ran their design through our system. We presented back to them out observations and recommendations that we came with by running our tool. They looked at what we had done and said “You did that in six weeks! We took six months to come up with the same set of things.” They were quote unquote sold at that instant that this was a tool that could provide real value in their process.

At the beginning we are going to be proving to people on a benchmark level. They are going to have to see it to believe it. It's the traditional software process. As you announce success stories and reference accounts other companies will say “If they are doing it, we want to do it also.”

It can be difficult to get reference accounts.
You are absolutely right. Some people don't want to and some people do. Fortunately there are enough who do. I don't see it as an issue. If you visit enough websites in particular EDA companies you will see that there are lots of people willing to be references.

What is your biggest challenge over the next 12 months?
For a small company to is usually bandwidth; getting the bandwidth so that you can engage with people efficiently. That's probably the biggest challenge.

Do you have enough sales people on board to meet that challenge?
I think we are where we need to be right now. We see some growth coming our way as products and references are announced. We've got plans to staff up. As a venture backed software company, it is always a difficult to ensure that you are using the cash in the most effective manner. You use that to bring in more revenue and help provide more investment in the product and in the sales channel. I think we are now exactly where we want to be. As the product gets announced and gets deployed we should be able to staff up. I don't see that as any kind of a barrier but rather a natural progression.

Alex Alexanian who founded Mosaic Systems, is the President and CEO of Ponte Solutions. How is he to work for?
We are all engineers by background. We communicate very well, high bandwidth which is great. He is a great guy, very knowledgeable about the engineering side. On a personal level he is open to learning about building a business rapidly. He is a decisive kind of guy, so a good leader. The whole Armenian connection is unique with us. There is a lot of talent in Armenia. There are probably only a handful of people here in Silicon Valley who could have taped that. It's fortunate that he had that ability to go do that.

The top articles over the last two weeks as determined by the number of readers were

Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models Mentor announced the release of the ICX and ICX Pro Signal Integrity Design Kits for Intel's next generation I/O controller hub. This kit is the first to utilize Intel's new IBIS 4.1 and IEEE 1076.1 standard VHDL-AMS models.

Magma Reports Record Revenue of $41.3 Million in Third-Quarter Financial Results Magma Design Automation Inc. announced it achieved record revenue of $41.3 million for its 2006 fiscal third quarter, ended Jan. 1, 2006, an increase of 11% over the $37.3 million reported for the year-ago third quarter.

Synplicity Announces Fourth Quarter and 2005 Results Sequence revenue for the year was $61.9 million, a 9 % increase from revenue of $57.0 million for 2004. Revenue for the quarter was $16.3 million, an 8% increase from revenue of $15.1 million in the foruth quarter of 2004.

Cadence Reports Q4 Revenue Up 10% Over Q4 2004 Cadence reported fourth quarter 2005 revenue of $378 million, an increase of 10% over the $343 million reported for the same period in 2004. Cadence recognized net income of $27 million, compared to $60 million a year earlier. Revenues for the fiscal year 2005 totaled $1.33 billion, an increase of 11% over the $1.2 billion in 2004. Net income for the fiscal year 2005 was $49 million compared to net income of $74 million for the year 2004

ProDesign Reports Record Growth for 2005; Increasing Demand for CHIPit Verification Systems Resulted in Most Successful Fiscal Year in Company History Revenue increased by more than 30% between 2004 and 2005. Driving this growth was the CHIPit ASIC Verification System business unit which increased their revenues by, 100% in just one year.

Other EDA News

Cadence Board Authorizes $500 Million Stock Repurchase

MEDIA ADVISORY/VaST Demonstrates Virtual Prototyping Leadership at Embedded World

AWR Posts Record Sales, Closes Third Round Financing MatrixOne Reports Financial Results for Second Quarter of Fiscal 2006; Company to Host Conference Call and Webcast at 5:00 PM Eastern Time

Computing Future, FPGA Programming Power and Performance at DATE; Celoxica And Other Industry Leaders Outline FPGA-Based Solutions Delivering High-Performance Computing At Europe's Leading Electronics Design Event

Nascentric to Use United Devices' Grid MP for Simulation and Verification Clusters; Nascim(R) Leverages Grid MP for Chip-Level Simulation and Verification

Broadcom to Use Interra's H.264 Analyzer

ARM and Handshake Solutions Announce Availability of Industry's First Clockless Processor for Real-Time Chip Designs

ADVISORY/Synopsys to Deliver Keynote, Lead SystemVerilog Tutorials at DVCon 2006

Synopsys' Pioneer-NTB SystemVerilog Testbench Automation Wins IEC DesignVision Award

Cadence X Architecture Design Solution Wins 2006 IEC DesignVision Award; Industry's First IC Physical Implementation System for X Architecture Awarded Top Honor in ASIC and IC Design Tool Category

Synopsys Professional Services Adopts Giga Scale ICs InCyte™ Chip Estimation System

ESS Technology Licenses Kilopass XPM Memory Technology

Real Intent Integrates Novas Debug Capabilities, Creating Highest Efficiency Formal Verification Solutions

Magma's IC Implementation Flow Minimizes Turnaround Time and Power for Complex 65-nm Designs; Blast Fusion Proven to Deliver Predictable Timing and Ensure Design Rule Compliance on Multimillion-Gate ICs

MatrixOne to Host Seminars on Environmental Compliance for Electronics Companies; Seminars on RoHS Regulation to Take Place in Massachusetts and California

Mentor Graphics Announces Support for Intel's IBIS 4.1 AMS Signal Integrity Models

Reminder - Kilopass Invites Electronic Design Community to DesignCon to Learn About Embedded Non-Volatile Memory Applications for Standard Logic CMOS-Process Designs

Sigrity Enters IC Package Physical Design Market by Acquiring Technology License from Synopsys; Provides Full Spectrum of Tools to Tackle IC Package Design and Analysis Challenges

Jasper Design Automation Names Claudionor Coelho as Vice President of Engineering; Formal Industry Veteran to Lead Growing Multi-National Engineering Team Located in US, Sweden and Brazil

Sequence Chosen By Genesis Microchip For Voltage Drop and Power-Grid Integrity

Sigrity Enters IC Package Physical Design Market by Acquiring Technology License from Synopsys

Tanner EDA Announces Its Latest T-Spice Pro with Support for New Industry-Standard Transistor Models; T-Spice Pro v11.2 Includes Support for the Penn State Philips (PSP) Model Chosen by Compact Model Council (CMC) and Other New Features

Gradient Design Automations FireBolt™ Selected as Finalist for DesignVision Award

Synopsys Professional Services Adopts Giga Scale IC's InCyte(TM) Chip Estimation System

Apache's PsiWinder Named Finalist for EDN Innovation of the Year Awards

Denali CEO Sanjay Srivastava to Speak at ISA Vision Summit

u-Nav Microelectronics Picks Tensilica's Xtensa Processors for Portable GPS Systems; Low Power Was Key Criteria for u-Nav's Choice of Xtensa Processors

CoWare Adds MIPS32(R) 34K(TM) Processor Support Package to SystemC-based Model Library; Expansion of CoWare Model Library Enables Development of Optimal Architectures for MIPS32 34K-based Systems

MatrixOne to Release Second Quarter Financial Results on February 8, 2006

Synopsys' New Designware USB 2.0 nanoPHY IP to Cut Power and Size in Half

LogicVision Announces Next-Generation Yield Analysis Automation Solution

Reminder - Real Intent's Verix Software Honored as DesignVision Award Finalist; See Formal Verification From Spec to Sign-off at DesignCon

Synplicity's FPGA Physical Synthesis Solution Selected as an EDN Innovation Award Finalist; The Synplify Premier Software Selected from a Field of Hundreds of Products

Cadence Virtuoso Speeds Design and Verification of Sirific's 3.5G Cellular Transceivers; UltraSim Cuts Verification Time From Weeks to Hours

Bluespec Executives to Participate This Week in DesignCon Tutorial Session, Management Forum

EVE to Exhibit Hardware-Assisted Verification Platform at DesignCon; Continuous Demonstrations of ZeBu Planned

Other IP & SoC News

IXYS' Clare Subsidiary Expands AC-Power Switch Family by Offering 600V and 800V Devices for Improved Power Control and Efficiency

Newport Media Demonstrates Breakthrough Single-Chip Technology for Mobile Digital Television; 3GSM World Congress Demonstration of Sundance Series(TM) Platform Features Leadership Technology

STMicroelectronics Releases Single-Chip SXGA Camera Module for Mobile Phones

Atheros Communications Delivers a Cellular/Wi-Fi Connectivity Solution Compatible with QUALCOMM Chipsets

ITC Investigates SanDisk's Complaint Against STMicroelectronics; Actions Seek to Stop Sale of ST's NAND and NOR Chips

Micron Technology, Inc., Announces Company Reorganization; Changes Reflect Focus on Furthering Success of Product Diversification Efforts

Analog Devices Reports Results for the First Quarter of Fiscal Year 2006

TriQuint Semiconductor, Inc. Announces Results for the Quarter and Year Ended December 31, 2005

Sipex Files Patent Application for Programmable Digital Power Controller

New Ultra-Miniature Crystal Clock Oscillators Enable Smaller Platforms, More Features

Zarlink Introduces Carrier-Class Synchronization Chip for AdvancedTCA, AMC and MicroTCA Applications

MagnaChip Semiconductor Launches High-Performance 1.3 Megapixel CMOS Image Sensor SOC

STMicroelectronics Announces Wireless LAN Chip for Wi-Fi Enabled Mobile Phones

UMC Reports Sales for January 2006

Amkor Reports Record Fourth Quarter Sales and Return to Profitability

TriQuint Promotes Complete RF Front-End Design for WCDMA / EDGE Handsets

Cypress Transfers SPLDs, MAX340(TM) CPLDs, and FLASH370i(TM) CPLDs to Arrow/Zeus Electronics, Ensuring Supply and Long-Term Product Support

Texas Instruments, MIT, DARPA Collaboration Results in Industry's Lowest Voltage 65-nm SRAM

Lattice Semiconductor Launches LatticeSC System Chip FPGA Family

Lattice Expands Market for Low Cost FPGAs With 90nm LatticeECP2 Family

Cypress Acquires Its Cypress MicroSystems Subsidiary; Company Buys Out Minority Interest in Fast-Growing Programmable System-on-Chip(TM) Enterprise

GCT Semiconductor Commercializes World's First Highly Integrated CMOS Single-Chip Tuner for Mobile TV Applications; Latest Industry Innovation in Production with a Top Korean Handset Manufacturer

STMicroelectronics Introduces Highly Integrated Power Management Chip Maximizing Battery Life for Portable Multimedia Systems

Low Power Asynchronous Audio Codec from STMicroelectronics is Optimized for Mobile Phones and Handheld Multimedia Players

Advanced Semiconductor Engineering, Inc. Reports Consolidated Year 2005 Fourth-Quarter and Full-Year Financial Results

SiRF Launches New Architecture to Significantly Shrink GPS for Mobile Phones

Best Innovators of Electronic Design Honored at DesignCon 2006

Cadence X Architecture Design Solution Wins 2006 IEC DesignVision Award; Industry's First IC Physical Implementation System for X Architecture Awarded Top Honor in ASIC and IC Design Tool Category

Fairchild Semiconductor's High-Bandwidth HDMI Switch Allows Designers to Easily Upgrade Existing Display Products for Multiple-Application Connectivity

Cypress to Present "PSoC(R) CapSense World Tour 2006" Seminar Series in Over 55 Cities in North America and Europe

Avago Technologies Adds Wide-Ranging, Knowledge-Base Tool to Web Site; New Application Provides Repository of Answers to Customer Questions

Vishay Reports Results for Year and Fourth Quarter 2005

Atmel Announces WiMAX Specific Transceiver

Altera and TelASIC Announce Breakthrough Power Efficiency for 3G/3.5G Wireless Base Station Radios

Sequans Announces World's First WiMAX Forum Certified(TM) Base Station and Subscriber Station Reference Designs

iRoC Launches Its Professional Service for Soft Error Risk-Free Designs; SERPRO(TM) Assists Design Centers Match Upcoming SER Specifications From System Houses With a Team of Experts Combined With a Unique Toolbox

Xilinx Ships FPGA Industry's Only Compliant Programmable x8 PCI Express IP Core

Denali Appoints Raju Pudota as Managing Director of India Subsidiary

Quellan Chips Deliver Up to 300% Improvement in Speed or Reach to Data Center Interconnects

SanDisk Opens Flash Memory Design Center in India; R & D Facility in Bangalore Will Work on Key Components of SanDisk Products

AMD Announces Broad Availability of Its I/O Virtualization Technology Specification; Open License Continues x86-Based Virtualization Momentum

Conexant Announces Unfavorable Outcome in First Phase of GlobespanVirata-Derived Litigation with Texas Instruments; Federal Jury Affirms Patent Infringement Counterclaims; Second Phase of Case to Follow

Oki Electric Launches Voice Synthesis Chip with P2ROM(TM), Reducing Delivery Time to One-Third

Pericom Semiconductor Reports Fiscal 2006 Second Quarter Results

TTPCom and Analog Devices Announce Pre-Integrated Software Packages for Multimedia Handsets; Accelerates time-to-market for multimedia featurephones based on Analog Devices' SoftFone Chipsets

Infineon Describes Innovative Memory Circuits at ISSCC 2006

SMIC Reports 2005 Fourth Quarter Results

Microtune Taking Production Orders for DVB-H Tuner Chip; Announces First Volume-Production Order

Avago Technologies Expands Line of 3.3 V, 15 MBd Multi-Channel Optocouplers in Thin SOIC Package; Multiple Unidirectional and Bi-directional Channels Reduce Parts Count, Board Space and System Cost

Cypress Delivers Programmable Spread Spectrum Clock Oscillator With Embedded Crystal in Industry-Standard 5.0 x 3.2-mm LCC Package and Pinout; Pre-Matched Crystal Saves Design Time and Cost; Small Package Saves Board Space

Xceive's TV Tuner First to Receive ISF Certification; Designation Illustrates Xceive's Commitment to Offering Highest Performing Products in the Industry

Power Analog Microelectronics Announces Completion of Series A Financing

Fujitsu to Highlight New 65-Nanometer Process Technologies, 10 Gigabit Ethernet and the WiMAX SoC at Annual DesignCon 2006, Booth 641

Scintera Names Technology Veteran Arthur Reidel Chief Executive Officer

Altera's Stratix II FPGAs Enable 667-Mbps DDR2 SDRAM Data Rate

National Semiconductor's Latest RF Synthesizers Lead Industry With Lowest Power Consumption, Best System Performance

National Semiconductor Introduces Industry's First Synchronous, Monolithic, 1.5A Buck Regulator With Inputs up to 36V

Lightspeed Launches Reconfigurable IP Technology Offering

Rambus Introduces New Innovative Decision Feedback Equalization Technology; SmartDFE(TM) Achieves Substantial Cost Savings and Performance Increase

DiBcom Introduces New Optimized Integrated Solution for DVB-H Reception; DIB7070-H Includes an Internally Developed RF Tuner

Micron Technology, Inc. Introduces Smaller 2-Megapixel Image Sensor for Today's Popular Thin Phones; The World's First Image Sensor to Incorporate MIPI CSI-2 Standard; Micron to Showcase Complete Sensor Portfolio at 2006 3GSM World Congress

Xilinx Announces PlanAhead 8.1, Delivering a Two Speed-Grade Advantage Over Competing Solutions

ANADIGICS Reports Fourth Quarter and Fiscal Year 2005 Results

STMicroelectronics Reports World Record for NAND Flash Data Throughput

Elpida Memory Establishes Global DRAM Design Centers in India, Japan and U.S.A.; Edison Semiconductor Pvt. Ltd. Established in Bangalore, India

Tower Semiconductor Manufactures Wireless LAN Chips for Atheros Communications