Azuro’s Low Power CTS Tool Included in TSMC’s Second Integrated Sign-off Flow Release

Fully Scripted Grab-It-and-Go RTL to GDSII Design Flow Combines PowerCentric With Both Cadence and Synopsys P&R Tools to Deliver Seamless Integration for Clock Power Reduction

SANTA CLARA, Calif. — (BUSINESS WIRE) — April 12, 2010 — Azuro, Inc., a leading provider of advanced clock tree synthesis and timing optimization tools for digital chip design, today announced the inclusion of its PowerCentric™ low power clock tree synthesis tool in the second release of TSMC’s Integrated Sign-off Flow (ISF) in 65nm. The ISF is an automated RTL to GDSII chip implementation flow that tightly integrates TSMC foundry technology files, pre-qualified library, IP, EDA tools, and sign-off margin recommendations into a fully automated scripted production-quality flow that has been proven and refined over hundreds of applications. With this second release of the ISF, TSMC customers are able to tapeout with PowerCentric using either a Cadence or Synopsys based P&R flow and reduce clock power by 25% or more.

“Rising design setup costs and design cycle times are critical challenges for the semiconductor industry,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC. “With this second ISF release, TSMC is offering its customers a choice between Synopsys and Cadence P&R tools while maintaining the same high standards in silicon quality and design turnaround time.”

Building on the success of the first ISF release based on a Synopsys P&R tool, Azuro and TSMC continued to work closely together during the development and beta testing of a Cadence P&R based ISF to ensure that the insertion of PowerCentric into this flow was also completely transparent to its users. Using the ISF, chip design teams taping out to TSMC’s foundries can now exploit PowerCentric to reduce clock power within an extensively pre-tested pre-integrated production-ready flow including a full set of automated scripts and user documentation for either the Cadence or Synopsys P&R tools. “Collaboration between EDA vendors and foundries is vital to continued growth and profitability of the chip design industry,” said Paul Cunningham, co-founder and CEO of Azuro. “With this second ISF release TSMC is dramatically reducing the cost and time to tapeout for large chip companies and small chip startups – and they are doing this without any sacrifice in silicon quality. The seamless grab-it-and-go integration of PowerCentric into ISF while expanding its P&R tool support is a perfect example of the benefits of their ecosystem driven approach.”

About PowerCentric™

PowerCentric is a clock tree synthesis tool for digital standard cell based chip designs. It reduces chip power by up to 20% and dramatically increases designer productivity on designs with complex clock networks.

About Azuro

Azuro is an electronic design automation company supplying software tools for use designing digital semiconductor chips. The company's unique clock tree synthesis and timing optimization technologies make chips faster, reduce chip power and dramatically accelerate chip time to market. Founded in 2002, the company is headquartered in Santa Clara, CA with R&D in Cambridge, UK, and is privately held. For additional information, visit http://www.azuro.com/



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