Virage Logic IP Times July 2009 and DAC Preview


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July 2009 – DAC Preview

Welcome to the July issue of IP Times – your source for semiconductor Intellectual Property (IP) news, trends, and developments – from the industry’s trusted IP partner. See what Virage Logic has planned for the 2009 Design Automation Conference (DAC) coming up in San Francisco, California.

Resource Center

Issues in SoC Methodology
Although statistical design methodology and modeling offers enormous potential, designers may not be ready to fully deploy this methodology at the SoC level. We don’t even know all the possible pitfalls yet, but here is a list of some important questions to consider… Go to the Vipster Blog.

Virage Logic in the News

Virage Logic Offers Broadest Portfolio of Embedded Non-Volatile Memory Solutions at TSMC
Virage Logic announced that it offers the broadest portfolio of embedded non-volatile memory (NVM) at TSMC, with fully qualified IP solutions ranging from 250nm down to 65nm. With a comprehensive selection of multi-time programmable (MTP) and few-time programmable (FTP) NVM IP, the AEON® product family addresses the needs of wireless, automotive, analog, power management and security applications. Read more.

Virage Logic Sees Strong Adoption of Company’s Broad 40nm IP Product Portfolio
Since being named TSMC's 40nm early development partner in 2007, the company has seen strong adoption of its extensive 40nm product portfolio. Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the Company's silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield. Learn how you can find the Sure Path to 40nm Success. Read more.

Virage Logic Expands Presence in India to Serve Growing Market Demand for Broad IP Portfolio
Virage Logic has expanded its presence in India with the appointment of CoreEL as its sales representative. CoreEL joins a growing global network of sales representatives that complement and expand the reach of Virage Logic's direct sales channel. Learn more.

Auto Industry Replaces Fuse Technology with Standard CMOS Based MTP; Adds Functionality, Testability and Reliability –
The automotive industry has always set the bar in terms of quality and reliability metrics. Yield issues that cause a production line to go down can cost a manufacturer millions of dollars per day, and a field failure that requires a product recall can run into the hundreds of millions of dollars. Read more.

Should Dual Rail Go Mainstream in Deep Nanometer Era? – Electronic Design
Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the variability at the cost of additional design efforts. Dual rail solutions appear to be complex, but several area, power, and performance tradeoffs can be made to simplify the design.  Read more.

Memory Interface IP Sector Heats Up – EE Times
Virage Logic and other memory interface IP vendors are now seeing an upswing in business, analysts said. The severe downturn is causing a growing number of OEMs to evaluate or rationalize their internal IP efforts. Read more.

AEON® Memory Technology Gets Automotive Qualification – EE Times
The non-volatile AEON memory technology has been qualified for automotive use according to the AEC-Q100 standard. The technology could compete with certain applications where hitherto EEPROMs and Flash memory has been used.   Read more.

Non-Volatile Memory Qualified for Rigorous Automotive Standard – Electronic Design
Virage Logic’s AEON multi-time programmable (MTP) non-volatile memory (NVM) solution is the first qualified to the stringent quality and reliability standards of the automotive industry using only standard CMOS processing. Automotive integrated circuits (ICs) demand reliability and qualification testing above and beyond the requirements of typical consumer or industrial applications. Read more.

Tool Automates Power Optimization of Embedded SoC Memories – Electronic Design
In developing PowerPro MG, Calypto worked closely with Virage Logic to ensure that the tool would support Virage Logic’s 40nm SiWare™ Memory compilers. The SiWare memories are highly configurable with options to control area, speed, power, and yield. From a power perspective, the memories offer multiple modes: a run mode, a standby mode (light sleep), a shutdown mode, and a dormant mode (deep sleep). Read more.

Upcoming Industry Events

As the industry’s trusted semiconductor IP partner, Virage Logic participates in a variety of global industry events to help educate the SoC design community on the latest advanced IP technology. See below for a list of upcoming events where you can hear Virage Logic’s IP experts address the complex issues facing the industry today.

Design Automation Conference (DAC)
July 27-30, 2009
Moscone Convention Center, San Francisco, California

TSMC Open Innovation Forum – Booth #822
The Virage Logic IP experts will be exhibiting and speaking at DAC in the TSMC Open Innovation Forum booth to highlight the latest developments in advanced IP technology. Learn how you can take the Sure Path to 40nm Success – stop by to meet the team and hear more about our embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and DDR/interface IP solutions. Visit our website for more information about Virage Logic at DAC. Sign up today to attend DAC in San Francisco. Register.

Learn more about Virage Logic at one of these interactive panels or informative sessions at DAC:

Virage Logic Showcases Silicon Proven Advanced IP Solutions for TSMC Processes
Featuring SiWare™ Memory and SiWare™ Logic Solutions

Monday, July 27, 11:00am – 11:15am, TSMC OIP Stage Booth #822

IC Design Central Partner Pavilion Stage – Low Power Design
Innovative Power Optimized Memory for Advanced Node SoC Design
Monday, July 27, 3:00 – 3:30pm, ICDC Stage North Hall

Virage Logic Showcases Silicon Proven Advanced IP Solutions for TSMC Processes
Featuring AEON® and NOVeA® Non-Volatile Memory Solutions

Tuesday, July 28, 10:00am – 10:15am, TSMC OIP Stage Booth #822

DAC Management Day Track
Tuesday, July 28, 10:30am – 6:00pm, Room #131

Low-Power: Consumer Electronics’ Catch-22
Tuesday, July 28, 11:30am – 12:15pm, Booth #1928

DFM – Band-Aid or Competitive Weapon?
Wednesday, July 29, 9:00am – 11:00am, Room #131

Virage Logic Showcases Silicon Proven Advanced IP Solutions for TSMC Processes  
Featuring Intelli™ DDR and PCIe Advanced Interface IP Product Solutions

Wednesday, July 29, 10:00am – 10:15am, TSMC OIP Stage Booth #822

Chip Estimate – IP Talks! – Virage Logic Overview
Wednesday, July 29, 10:00am – 10:20am, Booth #1100 South Hall

Virage Logic Showcases Silicon Proven Advanced IP Solutions for TSMC Processes
Featuring STAR™ Memory System and STAR™ Yield Accelerator Solutions

Wednesday, July 29, 2:00pm – 2:15pm, TSMC OIP Booth #822

International Symposium on Low Power Electronics and Design 2009 (ISLPED 2009)
August 19-21, 2009
The Westin Hotel San Francisco Airport, Millbrae, California
Dr. Yankin Tanurhan, Vice President and General Manager of Virage Logic’s NVM Business, will be giving a keynote presentation on “Dealing with Disaggregation in the Ever-changing World of Semiconductors.”   Register.

Upcoming VIP Partner Events

Virage Logic’s VIP Partner Program brings together technology and business alliances with our industry partners for the benefit of our mutual customers. As part of the VIP Partner Program, Virage Logic supports our partners’ global events, such as the ones listed below.

Synopsys Users Group (SNUG) Singapore 2009
Sheraton Towers Singapore  
August 18, 2009 – Singapore
Visit Virage Logic at SNUG, an open forum to exchange ideas and explore solutions that focus on real-world design challenges. Meet with Virage Logic’s experts for advanced technology IP solutions. Learn how Virage Logic can help you accelerate your time-to-market with production proven technology. Register.

Virage Logic Membership Has its Access Privileges

Become a Virage Logic Member for exclusive access to Foundry-Sponsored IP, technical documentation, and much more! It only takes a few minutes to become a Virage Logic Member. Sign up today and begin enjoying the benefits of Virage Logic Membership.

Looking for some good beach reading this summer? – Take along IP Times!

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Virage  Logic Trusted Semiconductor IP Partner for SiWare TM Memory & SiWare TM Logic, ASAP TM Memory & ASAP TM Logic, STAR TM Memory System, STAR TM Yield Accelerator,  AEON (R) , NOVeA (R) , Intelli TM DDR, Intelli TM PHY+DLL & Intelli TM Models. Copyright © 2009 Virage Logic.
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