A Verific customer since 2003, DAFCA –– for design automation of flexible chip architectures –– has integrated Verific’s software into its validation software that enables rapid system-on-chip (SoC) validation and debug. Verific’s SystemVerilog, Verilog and VHDL software suite of parsers, analyzers, elaborators, and netlist oriented database, serves as DAFCA’s ClearBlue™ front-end for exploring, navigating, analyzing, documenting and modifying designs. All are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.
“The Verific technology has been a decisive part of our success,” affirms Dr. Peter L. Levin, DAFCA’s chief executive officer. “Moreover, they are extremely cooperative and responsive, and we never have to ‘ask twice’ for deliverables they have promised. It is a great relationship.”
Adds Rob Dekker, Verific’s president: “DAFCA has proven to be an EDA company to watch. We are delighted that our relationship with DAFCA is solid, strong and growing.”
DAFCA, Inc. is an electronic system validation software company that offers a framework for the design and implementation of on-chip system validation protocols. DAFCA’s ClearBlue™ product family provides at-speed visibility and transaction control with a library of compact reprogrammable instruments that are seamlessly inserted into RTL, pre-silicon. ClearBlue’s off-chip analysis software configures, operates and dynamically controls our infrastructure IP, which can be memory mapped to support hardware-software co-validation. DAFCA’s customers move seamlessly between simulation, emulation and FPGA-prototype environments –– in addition to final silicon –– without special pins or cell libraries. ClearBlue is compatible by design with all major EDA tool flows. More information can be found at www.dafca.com.
About Verific Design Automation
Verific Design Automation, with offices in Kolkata, India, and Alameda, Calif., is a leading provider of Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 30,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.
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Public Relations for Verific
Nanette Collins, 617-437-1822