STARCAD-CEL addresses the challenges of very advanced process technologies including 65nm, 45nm and 32nm. The STARCAD-CEL design methodology is shared amongst the top Japanese semiconductor companies that comprise STARC's membership as a standard digital design platform.
According to Nobuyuki Nishiguchi, vice president and general manager, Development Department-1 at STARC, CoolTime-PGA's rush current and wakeup time analysis for MTCMOS designs achieved near-perfect correlation with SPICE simulations in a mere fraction of the time. "CoolTime-PGA is a fast, accurate analysis engine that will be a fine complement to other outstanding technologies in the STARCAD-CEL flow."
CoolTime offers a fast "what-if" PGA capability that enables users to rapidly determine switch turn-on sequence to control peak rush current and minimize wake-up time. Rush current analysis examines the peak current required by a gated block as it turns on, and calculates the impact of this current on the power grid to other active sections of the chip. Wake-up time analysis determines how long it takes for instances in the power-gated block to reach the nominal supply voltage and be function and timing ready. CoolTime's PGA capability provides "what-if" rush current and wake-up time analysis results within an hour instead of the days consumed by conventional methods.
STARC is a research consortium of major Japanese semiconductor companies developing leading-edge system-on-chip (SoC) design methodologies. For more information: www.starc.jp/index-e.html
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets. For more information: sequencedesign.com.
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Jim Lochmiller, 541-821-3438