ATPG Starter Packages Improve Quality of ASICs; and Offer Accessibility and Affordability in Today's Changing ASIC Design EnvironmentSUNNYVALE, Calif.—(BUSINESS WIRE)—Oct. 15, 2004— Design-for-test (DFT) leader SynTest Technologies today announced that it is now offering DFT-PRO 100 and 200 Series of ATPG starter packages that will include the essential DFT tools for comprehensive ASIC testing. These tools will be able to operate on scan-inserted netlists and will include tools for testing DFT rules' violations, automatic test pattern generation (ATPG), as well as test pattern formatting to directly link to ATE from popular vendors such as Advantest, Agilent, Credence and Teradyne.
Experience has shown that to ensure a high quality of complex ASICs with respect to manufacturing faults and to shorten test development time, DFT methodology must be employed into ASIC designs.
Today, to curb costs, more and more large and small semiconductor companies are shifting the DFT insertion responsibility from dedicated DFT engineers to ASIC design engineers. Further, they are also increasingly out-sourcing the design activity to independent ASIC design houses. In case of ASIC design engineers, more than one engineer now needs to access the DFT tools at the same time. In case of ASIC design houses, usually strapped for cash, they now have to handle multiple projects simultaneously. In either case, the engineers cannot wait for tool licenses to become available. Consequently, they are all looking for unhindered accessibility to DFT tools for multiple users, and needless to say, with easy affordability.
"To facilitate inclusion of DFT at the design stage itself, without having to unduly burden financial resources, we are now offering the DFT-PRO 100 series of DFT tool packages," remarked L.-T. Wang, President and CEO of SynTest Technologies. He added, "With the affordable cost of these starter tool packages, our customers would be in a great position to recover their investment in the tools in a very short time, in many cases with their first design."
"Currently, we are offering two versions of the DFT-PRO 100 series. The DFT-PRO 100 is a basic package, while the DFT-PRO 200 is a package for chips with higher performance and shrinking geometries," said Ravi Apte, VP of Strategy and Business Development at SynTest. "We do not want availability of the DFT tools to become a bottle-neck for these design engineers or design houses, and are hence offering multiple license options at affordable prices. We expect this affordable pricing would also help designers of IPs to verify their fault coverage at the design stage itself."
About the DFT-PRO 100/200 Series
The DFT-PRO 100 package contains the following tools:
1. TurboCheck-Gate(TM) -- for DFT testability analysis at gate-level. It offers:
-- Immediate feedback about potential design and testability problems
-- Early detection of testability and synthesis constraint rule violations
2. TurboScan(TM)-ATPG -- for automatic test pattern generation for stuck-at, n-detect (multiple-detect), and Iddq fault models. It offers:
-- Advanced multiple clock domain handling using SynTest's proprietary multiple-capture-per-cycle scheme
-- Scan extraction of pre-synthesized scan chains. Hence, it can be used with scan chains inserted using third-party tools.
-- Very compact ATPG patterns, especially for multi-clock designs
-- Very high fault coverage using combinational ATPG
-- Can be used for distributed ATPG to shorten elapsed time
-- Generation of test vector sets for industry standard outputs such as STIL, Verilog, VHDL, or WGL
3. TesterOut(TM) -- formatter to output test vector sets in formats that directly link to ATE from Advantest, Agilent, Credence, and Teradyne.
The DFT-PRO 200 package is the basic DFT-PRO 100 package with additional support for transition and bridging fault models.
Packages and U.S. Pricing
DFT-PRO 100 Series
DFT-PRO 101: 1 license for 3 years -- $20K(a)
DFT-PRO 103: 3 licenses for 3 years -- $30K(a)
DFT-PRO 110: 10 licenses for 3 years -- $50K(a)
DFT-PRO 200 Series
DFT-PRO 201: 1 license for 3 years -- $30K(a)
DFT-PRO 203: 3 licenses for 3 years -- $45K(a)
DFT-PRO 210: 10 licenses for 3 years -- $75K(a)
(a) Single payment
SynTest Technologies, Inc., est. 1990, develops and markets advanced Design-for-Test (DFT) and Design-for-Debug/Diagnosis (DFD) tools throughout the world, to semiconductor companies, system houses and design service providers. The Company's products improve an electronic design's testability and fault coverage and result in reduced defect levels and reduced slippage in Time-to-Market (TTM). They also reduce overall design and test costs, by helping to reduce design iterations as well as the time and reloads on Automatic Test Equipment (ATE). These products include tools for logic BIST, memory BIST, boundary-scan synthesis, DFT testability analysis, VirtualScan synthesis and ATPG with XtremeCompact test vectors, concurrent fault simulation, silicon debug and diagnosis. The Company, headquartered in Sunnyvale, California, has offices in China, Taiwan, Korea and Japan, and distributors in Europe and Asia including Israel. More information is available at www.syntest.com.
SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: email@example.com
Acronyms: ATE: Automatic Test Equipment ATPG: Automatic Test Pattern Generation BIST: Built-In Self-Test BSD: Boundary-Scan Design DFD: Design for Debug/Diagnosis DFT: Design-for-Test IP: Intellectual Property SoC: System-on-Chip
TurboCheck-Gate, TurboScan, TesterOut, VirtualScan and XtremeCompact are trademarks of SynTest Technologies. All other company or product names are the registered trademarks or trademarks of their respective owners.
SynTest Technologies, Inc. Nayan Pradhan, 408-720-9956, ext. 301 Email Contact