"We build some of the world's largest and highest performance ICs and it's crucial for us to maintain design schedules in the face of increasing IC complexity," said Sameer Halepete, vice president of ASIC Engineering at NVIDIA. "We have used Olympus-SoC on multiple GPU tapeouts and are very impressed with the overall quality of results and design schedule savings."
At the heart of the Mentor Graphics® solution is the Olympus-SoC chip assembly flow, which combines the strengths of the conventional hierarchical and flat design flows to deliver high capacity, fast runtime, and reduced memory without sacrificing high quality of results. The inaccuracies and inefficiencies caused by physical partitioning of designs is eliminated by the Olympus-SoC product's innovative and scalable architecture that allows designers to load in multi-million gate designs flat, and close timing by working across the physical hierarchies, thereby minimizing ECO iterations.
Analysis and optimizations engines are based on a full chip, signoff-quality STA engine that natively handles timing and leakage power across any number of mode/corner scenarios. The physical SDC generation capability derives accurate block-level timing constraints from actual routes for interface paths. This eliminates the need to over-constrain the block timings with pessimistic estimations and significantly speeds up top-level closure. Synchronized optimization is another unique feature, which concurrently optimizes all replicated partitions in a full chip context to obtain better overall chip performance while maintaining complete consistency of the design. Finally, interconnect re-synthesis capability recovers late stage timing by reviewing pin assignment decisions incrementally during full chip optimization, and automatically adjusting pin assignments (location and layer) to improve overall performance.
"We are very pleased with NVIDIA's success and its decision to standardize on Olympus-SoC for physical implementation and optimization," said Pravin Madhani, general manager for the Place and Route group at Mentor Graphics. "Olympus-SoC's unique architecture, high capacity data model and efficient multi-corner, multi-mode design closure capabilities continue to drive its adoption across various IC growth segments such as mobile, wireless, networking and graphics."
About the Olympus-SoC Product
The Mentor® flagship Olympus-SoC place and route system comprehensively addresses the performance, capacity, time-to-market, and variability challenges of advanced digital IC physical design. It concurrently optimizes IC designs for variations in lithography, process corners, and design modes to deliver the best quality of results for timing, power, signal integrity and die size. The Olympus-SoC product is production proven in numerous tapeouts of the most advanced designs of leading fabless designers and IDMs in a wide variety of application segments.
Product highlights include the Olympus-SoC adaptive variability engine, multi-corner clock tree synthesis, UPF-based multi-voltage low power flow, open router architecture with Calibre® technology in the inner loop of the routing kernel, and advanced chip assembly capabilities. The Olympus-SoC system is built on a patented, open architecture and ultra-compact database that can deliver full chip design, assembly and optimization with fast turnaround for designs with hundreds of millions of gates. Fully-multithreaded analysis engines and the industry's only fully-parallelized timing and optimization engine provide near-linear speedup on multi-core and multi-CPU computing platforms.
About Mentor Graphics
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(Mentor Graphics, Mentor and Calibre are registered trademarks, and Olympus-SoC is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)
For more information, please contact: Gene Forte Mentor Graphics 503.685.1193 Email Contact Sonia Harrison Mentor Graphics 503.685.1165 Email Contact