Cadence Announces Industry's First Complete Environment for Gigabit-Speed PCB Systems Design

Innovations in Cadence(R) 15.0 Software Release Focus on Design, Analysis, Implementation of High-speed System Interconnect

SAN JOSE, Calif.--(BUSINESS WIRE)--July 21, 2003-- In an industry-first move to help designers meet the challenges of designing gigabit-speed PCB systems, Cadence Design Systems, Inc. (NYSE: CDN) today announced the Cadence(R) 15.0 printed circuit board (PCB) and integrated circuit (IC) packaging design environment. The release, available now, includes enhancements and innovations spanning the entire integrated flow.

Now, for the first time, engineers have a complete environment for designing and implementing gigabit serial interfaces in high-speed PCB systems through a simulation and constraint-driven differential interconnect implementation from die-to-die across all three system fabrics: silicon, IC Package, and PCB. This robust capability puts first-time design success within reach of computer and network companies.

Other productivity-enhancing advances include the following:

-- new capability for the automated design of stacked-die systems-in-packages (SiP);
-- unified and automated library part creation, validation and management, environment;
-- dynamic real-time copper pour, plow and editing; and
-- advanced simulation capabilities for signal integrity model verification.

"The gigabit interconnect technology that allows systems designers to meet market demand for more system bandwidth is causing a revolution in design at the board and IC package levels," said Charlie Giorgetti, corporate vice president and general manager of the Cadence PCB Systems Division. "Engineers are facing unprecedented signal integrity, timing and routing issues, compelling them to look across design domains and consider the high-speed interconnect from I/O cell-to-I/O cell across IC packages and PCBs."

Designing the Gigabit Serial Interconnect

Key to successful gigabit serial interface design is the creation, constraint, simulation and management of differential signals throughout the entire design flow. Features in the Allegro layout and SPECCTRAQuest signal design and analysis environments enable designers and engineers to reduce design cycles by introducing the ability to design a comprehensive set of rules within a constraint management system and then use those rules to drive layout and routing. This can eliminate numerous iterations and enables first-time design success.

Advanced Packaging Solution for Stacked-die Design and Analysis

As progressively more manufacturers turn to system-in-package (SiP) technology to reduce product footprint, integrate disparate technologies and reduce time to market, designing integral die stacks becomes increasingly attractive. A new multiple stacked-die design and editing environment and an automatic wirebond creation capability in the Cadence Advanced Package Designer speed the design process, helping manufacturers get products to volume production quickly.

"SiP technology offers incredible performance and cost advantages for manufacturers. Designers, however, face enormous challenges in creating the requisite complex stacked-die structures," said Bret Zahn, vice president of Worldwide Design and Characterization, ChipPAC Inc. "As the market leader in stacked-die package design, assembly, and test, ChipPAC uses the new Cadence capability to deliver the highest-performance and most cost-effective packaging solutions to our customers."

Automating Library Part Creation, Validation and Management

New capabilities in PCB Librarian Expert 15.0 address process bottlenecks created as librarians manually struggle to enter, create and validate component data for the large pincount devices common in today's designs. The new release advances electrical component library development and management through the following:

-- Use of XML for data-driven symbol generation, management and


-- The capability to import pin and package data directly from

Internet-available datasheets in .PDF or .CSV formats;

-- Online part validation to user-definable company standards,

ensuring that parts comply 100 percent to specification; and,

-- Automatic library management routines that track changes

between part versions, providing detailed reporting of

revision differences.

Dynamic Real-time Copper Pour

Outer-layer ground planes are pervasive in today's complex, high-speed PCB designs, commonly used for shielding, noise reduction and supplying selective power to sensitive sub-circuits. Today, creating and modifying such entities can be very time-consuming due to complex manufacturability requirements. Addressing this in Allegro 15.0 is a fast, easy-to-use solution for real-time copper pour that allows for dynamic plowing and healing during interactive or automatic routing. Importantly, the new feature allows shapes to be edited at any time -- without any need for re-creation or post-processing -- making ECO changes easy.

Model Integrity Environment

A new SPICE-to-IBIS Model Integrity module in the SPECCTRAQuest SI Expert solution helps users create IBIS models from SPICE models quickly. With the output of the SPICE simulation run, IBIS and Buffer options file, users can now create known good IBIS models quickly. Model Integrity identifies I-V and V-t tables for typical, maximum and minimum corner cases from the SPICE run file. Since the number of points in a SPICE simulation run could be far greater than the maximum number of points allowed in IBIS, Model Integrity SPICE-to-IBIS module applies an intelligent and proven best curve fitting algorithm to provide accurate IBIS models.

North American Pricing and Availability

The new release is supported on Solaris, HP-UX, IBM-AIX platforms, Windows 2000 and XP Pro. Pricing outside of North America, is available from local Cadence offices and distributors.

Product          Starting price  License  Included software
                  (U.S. list)
---------------- -------------- -------- -----------------------------
PCB Design         $4,000       1 year   Concept(R) HDL schematic or
 Studio                                   Capture (R)CIS schematic,
                                          library management, Allegro
                                          for interactive layout and
                                          SPECCTRA autorouter
---------------- -------------- -------- -----------------------------
PCB Design         $26,000      1 year   Concept HDL Expert or Capture
 Expert for                               CIS schematic, constraint
 high-speed                               and topology management,
 design                                   library management, Allegro
                                          Expert for interactive PCB
                                          layout and SPECCTRA Expert
---------------- -------------- -------- -----------------------------
SPECCTRAQuest      $24,200      1 year   Pre- and post-route topology
 Signal                                                           extraction  and  exploration,
  Integrity                                                                simulation  &  verification,
  Expert                                                                      constraint  and  topology
                                                                                    management,  virtual
                                                                                    floorplanning  and
                                                                                    interconnect  routing
----------------  --------------  --------  -----------------------------

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