Chartered Begins Production Ramp of Enhanced 65nm Low-Power Process; Improves Power Utilization by 30-50 Percent

SINGAPORE — (BUSINESS WIRE) — July 13, 2009 Chartered Semiconductor Manufacturing (Nasdaq: CHRT) and (SGX: CHARTEREDSC), one of the world’s top dedicated foundries, today announced the general availability of an enhanced version of its 65-nanometer (nm) low-power (LP) process, called 65nm LPe. The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent. The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.

Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: “Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications”).

The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X. This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.

A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic. The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.

“ARM is pleased to expand our long standing relationship with Chartered by offering a full complement of physical IP optimized for Chartered 65LPe process,” said Simon Segars, executive vice president and general manager PIPD division, ARM. “This rich platform of IP includes enhanced memories and logic targeted at improving the performance of ARM processors. All products are supported by the most advanced power management EDA views. We believe this combination of 65LPe process and ARM physical IP is well suited to a range of mainstream applications where leakage optimization is paramount. Through the sponsorship of Chartered, the libraries are free and available today at http://designstart.arm.com.”

“We have worked closely with Chartered to optimize our SiWare™ Memory and SiWare™ Logic solutions to their 65nm LPe process to meet our mutual customers’ SoC requirements,” said Brani Buric, vice president of marketing and sales at Virage Logic. “With a comprehensive dashboard of options, the SiWare product line provides the flexibility needed to efficiently manage design tradeoffs to meet low power as well as performance design requirements.”

Chartered’s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively. Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency. Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pMOSFET hole mobility and saturation velocity without detrimentally affecting the nMOSFET.

“Today’s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don’t compromise performance or functionality,” said Brian Klene, vice president, product marketing at Chartered. “Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based.”

Industry Support for Chartered 65nm LPe Process

“The Chartered 65nm LPe process is well-suited for the demands of power-sensitive mobile applications. With Analog Bits low-power, clocking macros, programmable interconnects and specialized memories, our customers can realize significant differentiation with high yield and reliability. We have a long heritage and well-proven track record of working closely with Chartered on each successive process generation, and we can optimize our product lines to work very efficiently with their underlying process. This helps streamline the design flow for designers and allows our technology to leverage the full potential of the advances Chartered has made in its manufacturing technology.”

– Mahesh Tirupattur
Executive VP
Analog Bits, Inc.
 

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