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* Magma Design Automation announced Talus 1.1, described as “a new RTL-to-GDSII chip implementation system that delivers the fastest timing closure on the largest and most complex semiconductor designs. Talus 1.1 utilizes the new Talus COre technology, which leverages Magma's unified data model to perform timing optimization concurrently during routing.”

* Magma also announced that NVIDIA is using the Talus 1.1 IC implementation system in full production.

* Mentor Graphics announced that Fujitsu Microelectronics “qualified and adopted Mentor’s Calibre design-to-silicon platform for physical verification and DFM of advanced IC products.”

* Mentor Graphics also announced PADS 9.0. Per the Press Release: “This significantly-enhanced release of the PADS flow adds new levels of functionality, scalability and integration … Functionality now integrated in the scalable flow includes the addition of manufacturing and collaboration tools, and the world’s most powerful thermal, signal and power integrity analysis, as well as many core design entry and layout enhancements.”

* Open Core Protocol International Partnership (OCP-IP) announced a new white paper discussing an approach to Performance Analysis of Network-on-Chip Architectures for Video SoCs. Per the Press Release: “The paper describes a typical video SoC system, and the traffic profiles for each of the processing engines providing performance analysis measures of interest. Using the performance analysis measurements provided, companies can easily and quickly determine the performance of the analyzed system.”

* PDTi announced that, the industry's first true SaaS hardware/software EDA tool, has been adopted by Nethra Imaging for the design of their latest multi-core SoC. Per the Press Release: “SpectaReg is an essential web-based register automation tool for software/hardware interface design … Specifications are easily read into the tool and matching hardware logic, hardware verification, firmware, documentation and more are all rapidly auto-generated from a single source.”

* Physware announced that the PhysWAVE 3D fullwave design tool “has been optimized to assist design of MIMO Antennas for RF front ends and wireless ASICS.”

* Richtek announced a “Worldwide Unlimited License for SmartSpice and Verilog-A” from Simucad Design Automation.

* Signal Integrity Software announced support for the NFP-32xx from Netronome Systems. The companies say they have worked together “to analyze and ensure the signal integrity on all the NFP-32xx high-speed network interfaces … The work performed by SiSoft has resulted in a set of layout guidelines that can be used by NFP-32xx users to accelerate implementation.”

* Silicon Image announced its SiI5923 SteelVine Series 3 Core storage processor and the SiI3723 SteelVine Series 3 Core SATA 1:2 port multiplier. Per the Press Release: “Key applications for these new single-chip solutions include PCs, DVRs, and consumer electronics motherboards, as well as storage enclosures.”

* Solido Design Automation announced a new application for its Variation Designer tool that the company says, “analyzes and solves well proximity effect problems that become major concerns at 90-nanometers and below. The new Solve Well Proximity application allows … designers to proactively address well-proximity effects during the circuit-design stage without area sacrifices or increased design time resulting from other approaches. For example, in a 90-nanometer power management system amplifier design, guard-banding area was reduced by 95 percent compared to the traditional methodology.”

* Synfora announced PICO Extreme Power, which the company says is “the industry’s first algorithmic synthesis tool to automatically minimize power consumption at the system-level based on a variety of techniques, including automatic multi-level clock gating insertion. Multi-level clock gating enables clock gating to be applied to a computation block in an application accelerator at any level in the hierarchy.”

* Synopsys and Actel announced a “multi-year extension” of their OEM agreement for FPGA design tools. Per the Press Release: “Actel maintains rights to provide Actel-specific versions of Synopsys' Synplify Pro, Identify and Synplify DSP software as part of the Libero IDE.”

* Synopsys announced the DesignWare SATA AHCI host and device digital controller IP for the SATA 6Gbps data transfer rate, as defined in the Serial ATA Revision 3.0 specification.

* Synopsys also announced that its DesignWare DDR3/2 PHY and digital controller IP is “the first DDR3 IP fully verified in test silicon at 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification.” The company says test chips were manufactured at 65 nanometers.

* Synopsys announced that Exar Corp. has chosen Synopsys as its “leading EDA partner … The Synopsys' Galaxy Implementation and Discovery Verification platforms will be Exar's key design environment for designs at 65-nanometers and below.”

* Synopsys also announced that Infineon Technologies used IC Compiler with Zroute technology “provided a near 100-percent redundant via rate, enabling leading-edge device reliability and allowing Infineon to successfully tape out the lead product of its high-performance automotive 32-bit microcontroller platform in an advanced embedded Flash technology.”

* Synopsys also announced that SMIC is using Synopsys' HSPICE circuit simulator and WaveView Analyzer for design and verification of 65-nanometer and 45-nanometer IP blocks, I/O circuitry, and standard cell characterization flows.

* Synopsys also announced that Fujitsu Microelectronics used the Galaxy Implementation Platform for low power digital electronics and mobile application ICs.

* Synopsys also announced that New Japan Radio Co., Ltd. used IC Compiler's multi-corner/multi-mode capability and enjoyed 2X faster design closure.

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