Bryant the Beer Guy & Your Plans for DAC
* Agilent Technologies also announced Advanced Design System (ADS) 2009 Update 1, “which integrates 3-D EM analysis, wireless standards-based design verification libraries, X-parameter* simulation, statistical design and yield optimization, and enhancements for MMIC design.”
* Agnisys Inc. announced a free version of its IDesignSpec, which creates correct-by-construction code from the specification without manual effort.
* ANSYS announced Siwave 4.0, which includes “new features for signal-integrity, power-integrity and electromagnetic compatibility testing.”
* austriamicrosystems announced analogbench, a “design, simulation, and analysis tool to evaluate the performance of austriamicrosystems’ DC-DC ICs … analogbench generates a design proposal tailored to meet the user’s requirements, automatically calculates external components, and configures the application circuit.”
* austriamicrosystems and Fraunhofer Institute for Integrated Circuits (IIS) announced they will co-develop a new generation of magnetic motion sensing ICs, which will be based on Fraunhofer’s HallinOne magnetic sensor technology. “This sensor technology allows measuring of magnetic fields in horizontal and vertical dimensions, providing magnitude and direction of the magnetic field at any measured point. The HallinOne sensor can be implemented in a standard CMOS process, and can be seamlessly integrated with signal processing on a single die.”
* Atrenta announced that STMicroelectronics is including Atrenta’s SpyGlass-MBIST insertion tool as part of its front-end design kit. Per the Press Release: “This kit is accessible to all ST design teams worldwide as well as STMicro’s ASIC customers.”
* AWR and Rohde & Schwarz announced AWR Connected, which integrates the capabilities of R&S WinIQSIM2 simulation software within its Visual System Simulator (VSS) system analysis software.”
* Berkeley Design Automation announced that Newport Media Inc. is using BDA’s Analog FastSPICE platform for all analog, mixed-signal, and RF verification.
* Cadence announced product capabilities that “provide design and implementation engineers with … predictability of chip performance, area, power consumption, cost, and time to market across [a] range of design activities, including system-level design and IP selection through final implementation and signoff. The features result from an integration of Cadence’s InCyte Chip Estimator and Encounter Digital Implementation System technologies. Per the Press Release: “Using the new Cadence solution, designers can quickly and accurately estimate die size, power and cost, including real-time IP and manufacturing process what-if analysis to ease IP selection and determine design architecture and feasibility.
Perhaps more importantly: “As a milestone in Cadence's open, multi-vendor approach to IP, the solution leverages the vast ecosystem of IP at the ChipEstimate.com portal where over 200 IP suppliers and foundries contribute data to enable this accurate what-if analysis capability.”
* Cadence also announced that Casio Computer is using the Cadence’s C-to-Silicon Compiler for high-level synthesis.
* Cadence also announced that Faraday Technology used the “CPF-enabled” Cadence Low-Power Solution to tape out 20+ low-power chip designs.
* Cadence Design Systems also announced that the Chinese Academy of Sciences Institute of Computing Technology is using the Incisive Xtreme III System for “accelerating the development of RTL design with a verification flow for its … 64 million+ gates Loongson III advanced multi-core microprocessor.”
* Calypto Design Systems announced that Casio will use Calypto’s SLEC in its ESL design flow for digital cameras.
* Denali Software announced that Netronome Systems used Denali Databahn PCI Express (PCIe) design cores, MMAV, and PureSpec verification IP to design their high-performance Network Flow Processor NFP-3240, which targets “unified computing architectures.”
* eASIC Corp. announced that ARM validated eASIC’s Cortex-A9 MPCore multicore processor using eASIC’s Nextreme NEW ASICs.
* The eBeam Initiative announced that steering group members D2S, e-Shuttle, and Fujitsu Microelectronics have validated the DFEB methodology for low-volume, 65-nanometer SOC designs. Per the Press Release: “D2S and Fujitsu Microelectronics worked on the design while e-Shuttle manufactured the test chip to confirm the DFEB technology for the 65-nm node.”
* EMA Design Automation announced version 3.0 of the EMA Component Information Portal, which the company says “provides access to the Newark electronic parts database through OrCAD Capture CIS.”
* EVE announced Fujitsu Microelectronics Solutions is using the ZeBu hardware-assisted verification platform for hardware-software co-design.
* Forte announced that Ricoh Corp. designed a multi-million gate SoC design for its latest commercial printing products using Forte’s Cynthesizer SystemC high-level synthesis software.
* Gemini Design Technology announced that advICo Microelectronics has standardized on Gemini’s GSim simulator for use in all its complex, high-performance mixed-signal designs.
* LFoundry announced a high performance PDK for A/MS electronic designs, developed using Tanner EDA's HiPer Silicon software, for its LF150 modular 0.15-µm Low Power and RF CMOS process. Per the Press Release: “This grants Tanner EDA customers access to Europe's leading pure-play foundry CMOS technology … LFoundry offers a cost-efficient rapid prototyping service, known as Multi-Project Wafer (MPW) with the most frequent schedule currently offered in the industry. LFoundry will provide special incentives to their initial customers requesting participation in the service through to July 2009.”
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