Synopsys Declares for SystemVerilog

by Peggy Aycinena

SAN JOSE, California -- Feb. 25, 2003 - Monday's keynote address at this year's Design & Verification Conference (DVCon) was delivered to a sold-out lunchtime crowd by Aart de Geus, chairman and CEO at Synopsys, Inc. In a wide-ranging presentation, de Geus positioned the current situation in IC design and verification - and the subsequent need for SystemVerilog - within the larger context of the disarray in geopolitics, the global economic downturn, a faltering semiconductor supply chain, and the increasing complexity of today's chips.

Noting that public speakers are advised to start with a joke, de Geus said there's nothing funny about today's problems in design and verification and started, instead, with an acknowledgement of the pressures under which the current generation of IC engineers are working. He said Chip Design 101 mandates that a company and its designers must differentiate product offerings through function, performance, power, form factor, and price, while keeping an eye all the while on the cost side of the design and production equation and simultaneously meeting time-to-market and time-to-volume requirements.

He said the pressures of attending to all of this means producing excellent product offerings despite a dramatic increase in economic stress, markedly increased manufacturing costs, and exploding design complexity driven by Moore's Law - "Moore's Law is alive, well and kicking! It's going like there's no tomorrow and, in fact, most of us have made a career out of it."

Setting the international stage within which his audience of design and verification engineers is working, de Geus said, "In politics today, the overhang of the Iraq situation is quite large, and though nobody can quite point to the exact results, it's causing pause in [corporate] decision makers."

He said that having only one superpower in the world requires a new balance of force to be found and that, until that equilibrium is established, many CEOs are slowing capital spending. Additionally, he said, worldwide over-capacity can be found in every industry from airline seats, to real estate - particularly in Silicon Valley, and semiconductor production: "Although we're starting to close the 2001/2002 gap between semiconductor production capacity and demand, several more fabs are coming on board this year."

Commenting on the cyclical nature of the semiconductor industry, de Geus observed that the 1985 downturn was the largest on record prior to the 2001/2002 dip. However, the most recent downturn is proving to be twice as deep and long as the 1985 setback. As a result, "There has been a total recasting of the semiconductor supply chain and the amount of pressure is enormous. The cost of under-utilized fabs is having a huge impact and, simultaneously, we're seeing delay in [design] projects because the market is not ready."

Meanwhile, de Geus said that as system-on-chip (SoC) devices became technically feasible and economically viable in the 1990's, they subsequently became ubiquitous in consumer products. Noting, however, the increasing cost of the semiconductor content within larger systems, he said, "Today, for instance, the cost of the electronics in an automobile vastly supercedes the cost of the metal in the car, but we can't keep going like this."

SoCs, he said, are now more than just an embedded system with a single processor, limited memory, and I/O functions. They are highly complex systems on a single chip, which are sophisticated, well integrated, and cost effective - but these designs are more difficult to perfect due to the timing closure and signal integrity problems associated with increased on-chip device density. And, de Geus added, increased complexity triggers exponential increases in verification challenges, as well as probabilistic issues in manufacturing.

Reviewing recent history, he said the move to greater device integration has been precipitated by shrinking process technologies, and that the move from 0.25 micron to 0.18 micron designs brought the verification crisis to the forefront. With mask costs today ranging from $1 million to $10 million, de Geus quoted widely held industry beliefs that costly re-spins due to fatal design errors are becoming untenable and, therefore, verification strategies and technologies must be brought up-to-speed to meet the current needs of complex, difficult-to-diagnose system chips.

He said that the industry believes that 60% to 70 % of the overall design effort is in the verification of the chip. "However," de Geus said, "high-level executives at semiconductor companies don't quite understand verification. All they know is that their chips are troubled."

He added that if innovation is going to continue for 0.13-micron designs at below - formal verification, testbench development, assertion strategies, property checking, codesign, and language considerations are all going to have to be integrated with other relevant verification solutions to "make it all work together."

Acknowledging the work of Peter Flake (at GenRad) and Phil Mooreby (at Gateway) in developing Verilog, de Geus gave a brief overview of one version of the history of the HDLs in use today. He highlighted Cadence's purchase of Gateway in the early 1990's - which converted the Verilog code to Cadence IP - and the subsequent push by the U.S. government to develop an open-source language for hardware design.

He commended Cadence for its eventual decision to make the Verilog code open source, while noting that the emergence of VHDL as a government-endorsed HDL was coincident with VHDL's growth in popularity in Europe throughout the 90's. The resulting situation, per de Geus, was "horrible and incredibly expensive. Hopefully, we won't have to repeat [the problem of supporting multiple languages] as we move forward in verification."

Recounting how Simon Davidman, Flake, and Mooreby went on to develop Superlog at CoDesign in the late 1990’s as a system-level design language based on Verilog, de Geus also noted that the bulk of the Superlog code was then donated to the industry-standards body, Accellera, and provided the foundation for SystemVerilog: "Clearly, the contributions of these gentlemen has been significant over time." Both Flake and Mooreby were in the audience and stood to accept a round of applause.

With the authors of Verilog in attendance, de Geus went on to describe the benefits of SystemVerilog: "SystemVerilog has emerged out of the momentum and excitement of having been based on work of long-established experts [in the field of language design]." He added that SystemVerilog version 3.1 includes unified assertions and is currently under review in hopes of being approved by Accellera by the DAC 2003 timeframe. Then he held up the wire-bound specs for V3.1 and said he had received the document just before lunch. "I reviewed it over lunch and it looks great," he said to laughter from the audience.

Addressing the issue of SystemC, the C-based system-design language that Synopsys has long supported, de Geus reiterated what many were saying in the technical sessions at DVCon: "The languages [SystemC and SystemVerilog] can develop in parallel, without controversy or discontinuity."

He said that at the transaction level or higher, the C or C++ type of constructs in SystemC can be used to define functionality, while on the RTL and implementation side, VHDL and Verilog will see a natural succession to SystemVerilog. He added, "The conciseness of SystemVerilog is its greatest benefit. It reduces the number of lines of code, combines testbench and assertions, and therefore reduces runtime and allows for more tests. "

He then went on at length to define and defend assertions as a means for enabling the new design paradigm, Design for Verification. He elaborated on the strategies by which SystemVerilog would enhance assertions-based design strategies and reminded his audience: "SystemVerilog is 100% compatible with Verilog!" He then added an impassioned please for "evolutionary revolution."

For anyone in the attendance who might have missed his point, de Geus was unequivocal, "I believe SystemVerilog is opening up a whole new age in design. We're totally committed to SystemVerilog for verification and synthesis. We'll put the full weight of our company behind this. We support the work of Accellera and hope that SystemVerilog will loosen the vice grip of pressure for engineers working in the industry today."

Visit now to experience an in-depth SystemVerilog seminar-on-demand presented by Accellera.

Review Article Be the first to review this article

Featured Video
Mechanical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
System Designer/Engineer for Bluewater at Southfield, Michigan
Mid-Level Mechanical Engineer for Kiewit at lenexa, Kansas
GIS Data Analyst for CostQuest Associates, Inc. at Cincinnati, Ohio
Geospatial Analyst/Programmer for LANDIQ at Sacramento, California
Product Manager for CHA Consulting, Inc. at Boston, Massachusetts
Upcoming Events
ESPRIT World 2018 at Indianapolis Marriott Downtown 350 West Maryland Street Indianapolis IN - Jun 11 - 15, 2018
HxGN LIVE 2018 at The Venetian Las Vegas NV - Jun 12 - 15, 2018
IMTS2018 International Manufacturing Tech Show at McCormick Place Chicago IL - Sep 10 - 15, 2018
4th International Conference on Sensors and Electronic Instrumentation Advances (SEIA' 2018) at Movenpick Hotel Amsterdam City Centre Amsterdam Netherlands - Sep 19 - 21, 2018
Kenesto: 30 day trial

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise