2X speedup, 50% Less Memory, and New Advanced Timing Sign-off Features
SANTA CLARA, CA - December 2, 2008 - Incentia Design Systems, Inc., a technology leader in nanometer timing analysis and design closure solutions, announced today the availability of the 2008.10 release of its TimeCraft™ timing analysis software. The release improves runtime and memory usage significantly when compared to its 2007.10 release. In addition, it adds advanced timing analysis features for nanometer design timing sign-off. TimeCraft has been widely used and taped out many complex nanometer designs. With this new release, TimeCraft effectively handles extremely large designs in excess of 50M gates using technology at 45nm and below.
As technologies continue to shrink and designs continue to grow in complexity and size, the need for performance improvement in timing analysis tools is inevitable. The TimeCraft 2008.10 release has achieved up to 2X runtime speedup and 50% memory usage reduction, compared to its previous 2007.10 version. The runtime speedup and memory reduction can be observed in all kinds of analysis flows, including SDF, SPEF, and advanced on-chip-variation (OCV). Furthermore, the multi-threaded version of TimeCraft called TimeCraft-MT is now available to fully utilize the multi-CPU and multi-core in nowadays machine configurations, and provide another dimension of runtime improvement. All these efforts significantly reduce total verification turnaround time and hence ensure your time-to-silicon schedule.
Process variations become significant and cannot be ignored in nanometer designs. To model process variations, TimeCraft supports both advanced OCV and statistical static timing analysis (SSTA). The advanced OCV (aka LOCV) considers random and systematic variations through level- and location-based OCV. It applies variable derating factors to different timing paths to eliminate excessive guard banding imposed by a single constant derating factor. The 2008.10 release further adds new features, such as various granularity controls to achieve higher accuracy and flexibility. On the other hand, SSTA considers variations statistically from cells and interconnects with sensitivities. TimeCraft-SSTA can take either CCS-VA or S-ECSM library format, and perform both path-based and block-based analysis and reports, based on user defined correlations. Its runtime, memory usage, and accuracy have been significantly improved in the 2008.10 release.
"Our customers have started to deploy the TimeCraft 2008.10 release, and observed performance and memory improvements in line with our expectation." said Arthur Wei, vice president of operation at Incentia. "TimeCraft still maintains its leadership position as the fastest STA on the market with its new release of TimeCraft 2008.10".
TimeCraft timing analysis software is available for evaluation now on Linux (32-bit and 64-bit) and Sun Solaris (32-bit and 64-bit) platforms.
Incentia Design Systems, Inc. is a leading Electronic Design Automation (EDA) tool provider of advanced Timing Analysis, Design Closure, and Logic Synthesis software for multi-million-gate nanometer designs. Incentia patented technologies provide the fastest Static Timing Analysis (STA) tool in the market today. Incentia's products are in use at leading semiconductor, fabless IC design, systems, and design service companies worldwide and have produced numerous successful tape-outs in different design application areas, such as communications, networking, wireless, chip-sets, consumer electronics, and multi-media. Incentia has offices in Santa Clara, California and Hsinchu Science Park, Taiwan, and distributors in Japan, China, India, Korea, and Israel. For more information, please visit www.incentia.com, email to Email Contact or call 408-727-8988.
Arthur Wei, Incentia Design Systems, Inc., 408-727-8988 X120, Email Contact