MoSys Announces Quad-Density Memory Technology; 1T-SRAM-Q Technology Enables New Levels of On-Chip Memory


Nikkei Memory Congress

SUNNYVALE, Calif. & TOKYO--(BUSINESS WIRE)--Dec. 16, 2002--MoSys, Inc. (Nasdaq: MOSY), the industry's leading provider of high density SoC embedded memory solutions, today introduced 1T-SRAM-Q(TM) (Quad density) technology which achieves four times the density of traditional SRAMs. This addition to the 1T-SRAM(R) technology addresses the industry's need for increasing memory density.

The market demands for lower power in consumer products and greater bandwidth in high performance products are driving the need for more on-chip memory. By combining MoSys' proven 1T-SRAM technology with its new Folded Area Capacitor(TM) (FAC(TM)), the Company has created the solution with 1T-SRAM-Q technology, doubling the density of 1T-SRAM memory. 1T-SRAM memory requires a single, non-critical mask addition to industry standard CMOS logic processes adding no more than 5% to the wafer processing cost.

"By introducing the 1T-SRAM-Q technology, MoSys has solidified its leadership position as an innovative supplier of memory in the embedded marketplace," commented Sherry Garber, Senior Vice President of Memory Products, Semico Research Corporation. "MoSys has recognized the need for higher density, lower power, embedded memory, combined with error correction features that could be fabbed on widely available logic processes. This is a product positioned for rapid adoption."

Building upon the proven 1T-SRAM-R(TM) technology, 1T-SRAM-Q memory includes MoSys' Transparent Error Correction(TM) (TEC(TM)) offering the benefits of eliminating laser repair, improving yield, reliability and soft error rate while doubling the density. The reduced area of 1T-SRAM-Q memory results in shorter internal signal paths thereby increasing the speed and lowering power consumption.

"Three years ago, MoSys launched its proprietary 1T-SRAM technology which doubled the density of embedded memory on standard logic processes. As anticipated, the market has continued to require even more on-chip memory and once again, with 1T-SRAM-Q, MoSys is delivering the technology, to address this need," stated Dr. Fu-Chieh Hsu, president and CEO of MoSys. "By leveraging the manufacturability of standard logic processes in combination with our production proven 1T-SRAM architecture, MoSys continues its commitment to our customers by delivering innovative embedded memory technologies required by SoC designers."

MoSys' patented Folded Area Capacitor technology reduces bit cell size by literally folding the 1T-SRAM gate oxide capacitor vertically down the STI sidewall so that it occupies less horizontal die area. The resulting bit cell sizes of 0.50 and 0.28 micron2 enable 1T-SRAM-Q memory to be used for integrating up to 128-Mbits or 256-Mbits of embedded memory in 0.13-micron and 90-nanometer processes respectively. This is achieved by using only one additional non-critical mask in the standard logic process. Most significantly, the additional processing does not add to the transistor thermal cycle, resulting in no change to the logic transistor characteristics. This avoids the need to re-characterize existing logic IP for integration in SoCs using 1T-SRAM-Q memory technology.

A Web cast product briefing and supporting materials on 1T-SRAM-Q are available at www.mosys.com in the investor relation's section.

Price and Availability

License and NRE pricing for designers using 1T-SRAM-Q memory will remain the same as existing 1T-SRAM technology. MoSys is currently engaged with initial adopters of 1T-SRAM-Q technology for anticipated sampling in 2Q 2003 and mass production late 2003. Contact MoSys for pricing details on specific memory configurations.

1T-SRAM Technical Background

1T-SRAM-Q memory technology is based on MoSys' patented 1T-SRAM technology, which offers a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in 1T-SRAM technologies results in much higher density memory than possible with traditional four or six transistor SRAMs while using the same standard logic manufacturing processes. 1T-SRAM technologies also offer the familiar, hidden refresh interface and high performance for random address access cycles associated with traditional SRAMs. In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it an ideal technology for embedding large memories in SoC designs. 1T-SRAM technologies are in volume production both in SoC products at MoSys' licensees, as well as in MoSys' standalone memories.

ABOUT MOSYS

Founded in 1991, MoSys (Nasdaq: MOSY), develops, licenses and markets innovative memory technology for semiconductors. MoSys licenses its 1T-SRAM memory technologies as intellectual property (IP) to semiconductor and system companies for the development of SoCs, which cover a wide range of applications including the communications and consumer electronics markets. Foundry partners enable MoSys to provide silicon-proven 1T-SRAM technologies to fabless semiconductor companies in a variety of processes. MoSys' Design Services Alliance (DSA) builds relationships with third-party design firms that enable MoSys to provide an embedded memory solution while accelerating 1T-SRAM technology's adoption and licensee's transition to production. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys' Web site at http://www.mosys.com.


1T-SRAM(R)is a MoSys trademark registered in the U.S. Patent and Trademark Office. Folded Area Capacitor(TM), FAC(TM), Transparent Error Correction(TM), TEC(TM), 1T-SRAM-R(TM)and 1T-SRAM-Q(TM)are trademarks of MoSys. All other trademarks or registered trademarks are the property of their respective owners.

"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Statements in this press release regarding MoSys, Inc.'s business which are not historical facts are "forward-looking statements" that involve risks and uncertainties. For a discussion of such risks and uncertainties, which could cause actual results to differ from those contained in the forward-looking statements, see "Risk Factors" in the Company's Annual Report or Form 10-K for the most recently ended fiscal year.

CONTACT: MoSys, Inc.
             K.T. Boyle, 408/731-1830
             
Email Contact
                or
             Shelton PR
             Katie Olivier, 972/239-5119 x142
             
Email Contact
                or
             MoSys, Inc.
             Mark Voll, 408/731-1846
             
Email Contact
                or
             Shelton IR
             Beverly Twing, 972/239-5119 x126
             
Email Contact



Review Article Be the first to review this article

Featured Video
Editorial
Jeff RoweJeff's MCAD Blogging
by Jeff Rowe
Siemens Goes ECAD With Mentor Graphics Acquisition
Jobs
Mechanical Engineer for IDEX Corporation at West Jordan,, UT
Senior Structural Engineer for Design Everest at San Francisco, CA
Business Partner Manager for Cityworks - Azteca Systems, LLC at Sandy, UT
GIS Analyst II for Air Worldwide at Boston, MA
Upcoming Events
Design & Manufacturing, Feb 7 - 9, 2017 Anaheim Convention Center, Anaheim, CA at Anaheim Convention Center Anaheim CA - Feb 7 - 9, 2017
Innorobo 2017 at Docks de Paris Paris France - May 16 - 18, 2017
Display Week 2017 at Los Angeles Convention Center 1201 S Figueroa St Los Angeles CA - May 21 - 26, 2017
SolidCAM: Program your CNCs directly inside your existing CAD system.



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise