"The collaboration between TSMC and Cadence delivers automated design technologies necessary for low-risk and fast time-to-volume at these advanced process nodes," said S.T. Juang, senior director of design infrastructure marketing at TSMC.
Cadence has worked with TSMC over multiple process generations to develop reference flows offering low-power design capabilities and advanced DFM methodologies. With Reference Flow 9.0, Cadence extends these capabilities to the foundry's 40nm process node with litho physical analysis and enhanced statistical static timing analysis capabilities, among others. In addition, the Cadence track of the TSMC Reference Flow has supported the Si2 Common Power Format (CPF) for more than a year, and now includes new features complementing the fully integrated Cadence® Low-Power Solution to help provide fast, accurate low-power design.
"What we are delivering today is a proven methodology that reduces risk and accelerates time-to-volume for advanced node and low-power designs," said Chi-Ping Hsu, corporate vice president of IC Digital and Power Forward at Cadence. "Our deep collaboration with TSMC extends from modeling manufacturing variation to silicon-correlated low-power techniques to improve manufacturability of high-volume chips."
The new Cadence track of the TSMC Reference Flow 9.0 features a transparent half-node design flow that supports TSMC's 40nm process technology. This includes support for 40nm place and route rules, a full design-for-test flow, joint yield calculation for leakage and timing, enhanced statistical signal integrity timing analysis, hierarchical lithographic physical, timing and leakage analysis, hierarchical and concurrent critical area analysis and optimization, CMP-aware block RC extraction, clock buffer placement optimization, multi-mode multi-corner analysis, and hierarchical dummy metal fill.
The Cadence track of TSMC's Reference Flow 9.0 provides advanced DFM, power, routing and simulation capabilities for 40nm process technology. The silicon-correlated technologies include:
-- Timing, LEF, Cap libraries and integrated Critical Area Analysis for physical implementation using Cadence SoC Encounter RTL-to-GDSII System, including RTL Compiler and Encounter Timing System -- TSMC qualified layout printability checking including hierarchical analysis and hot-spot detection using Cadence Litho Physical Analyzer and automated fixing using Cadence Chip Optimizer -- Chemical Mechanical Polishing (thickness) prediction using Cadence CMP Predictor for electrical hotspot detection -- Hierarchical CMP and hierarchical metal fill insertion using the SoC Encounter System and the DFM solution. -- Feature-scale VCMP-aware block and chip-level RC extraction using Cadence QRC Extraction -- Special coverage for macro modeling, I/O pad modeling, secondary power domains and hierarchical flows for IP reuse using the CPF-enabled, RTL-to- GDS II Low-Power Solution -- IR, EM and power analysis using the VoltageStorm® PE and DG Option. -- Advanced multi-mode, multi-corner clock-tree synthesis with dynamic IR drop reduction -- Thermal runaway analysis and thermal-aware static timing analysis using statistical static timing analysis -- XOR Compression, and True Time At-Speed ATPG using Encounter Test
TSMC recently contributed a chapter to the Power Forward Initiative publication, "A Practical Guide to Low-Power Design - User Experience with CPF," detailing the actual use of the Cadence low-power design methodology. The guide was published by the Power Forward Initiative in March 2008 and has been downloaded more than 2,500 times. This continuously updated online guide is freely available through the Power Forward Initiative website at www.powerforward.org.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence® software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com
Cadence, Encounter, Virtuoso and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. in the United States and other countries.
For more information, please contact: Dan Holden Cadence Design Systems, Inc. direct: 408.944.7457 Email Contact