Berkeley Design Automation's Analog FastSPICE Selected By Supercomputer Project For 45nm Verification

SANTA CLARA, Calif.—(BUSINESS WIRE)—February 20, 2008— Berkeley Design Automation Inc., provider of Precision Circuit Analysis(TM) technology for advanced analog and RF integrated circuits (ICs), today announced that the company's Analog FastSPICE(TM) circuit simulator has been selected for complex analog and mixed-signal block verification in a next-generation 45nm supercomputer chip developed by the University of Tokyo and RIKEN.

"Berkeley Design Automation verification tools are critical to the success of our next generation 45nm supercomputer project," said Professor Takashi Ikegami of the University of Tokyo. "Analog FastSPICE delivered accuracy that is as good or better than traditional SPICE 5x-10x faster on our complex analog and mixed-signal blocks. Since we cannot rely on digital fastSPICE approximations for these designs, Analog FastSPICE enables us to perform verification tasks that were previously impossible."

"Analog FastSPICE is allowing us to verify our analog and mixed-signal blocks faster than we thought possible," said Duraid Madina, also of the University of Tokyo. "Analog FastSPICE is not only faster and more accurate than our other SPICE tools - it is faster than digital fastSPICE tools that cannot handle our mixed-signal designs. In our testing, Analog FastSPICE was often 10x faster than the best traditional SPICE, while giving identical results. We never observed a difference greater than 0.15%."

Berkeley Design Automation tools include Analog FastSPICE(TM) circuit simulation, RF FastSPICE(TM) periodic analyzer, and PLL Noise Analyzer(TM). The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1% or less) while delivering 5x-10x higher performance and 5x-10x higher capacity. It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.

Design teams from top-10 semiconductor companies to leading startups use Berkeley Design Automation tools to solve big analog/RF verification problems. Typical applications include characterizing complex blocks (e.g., PLLs, ADCs, DC:DC converters, PHYs, Tx/Rx chains) and running performance simulation of full circuits (e.g., wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data converters, and power converters).

"We are delighted and honored to be selected by the consortium as the circuit simulator of choice for the 45nm MDGRAPE-4 supercomputing chip," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "Our selection by this distinguished team is once again proof that Berkeley Design Automation's Precision Circuit Analysis(TM) technology is essential for success in nanometer analog/RF design."

About Berkeley Design Automation

Berkeley Design Automation, Inc. is the recognized leader in advanced analog/RF verification. Its Precision Circuit Analysis technology combines the accuracy, performance, and capacity needed to verify GHz designs in nanometer-scale silicon. Berkeley Design Automation has received numerous awards including EDN Magazine's 2006 Innovation of the Year, the 2006 Red Herring 100 North America, and the 2007 Red Herring Global 100 Finalist. Founded in 2003, the company is funded by Woodside Fund, Bessemer Venture Partners, Matsushita Electric Industrial Co. Ltd., and NTT Corporation. For more information, see

Analog FastSPICE, RF FastSPICE, PLL Noise Analyzer, WaveCrave, and Precision Circuit Analysis are trademarks and Berkeley Design is a registered trademark of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.


PR for Berkeley Design Automation
Cayenne Communication LLC
Michelle Clancy, 252-940-0981
Email Contact

Review Article Be the first to review this article

Autodesk - DelCAM

Featured Video
Senior Mechanical Engineer for Verb Surgical at Mountain View, CA
CAD Systems Administrator for KLA-Tencor at Milpitas, CA
Principal Research Mechatronics Engineer for Verb Surgical at Mountain View, CA
Industrial Designer Intern – Spring 2017 for Nvidia at Santa Clara, CA
Lead Geospatial Analyst for Alion at McLean, VA
Upcoming Events
PI APPAREL Hong Kong 2017 at SHANGRI-LA KOWLOON 64 Mody Road Tsim Sha Tsui East Kowloon Hong Kong - Apr 5 - 6, 2017
SOLIDWORKS intro and hands on session – Slough at Baylis House, Slough, Berkshire, SL1 3PB Slough United Kingdom - Apr 7, 2017
PMTS 2017 at Greater Columbus Convention Center Exhibit Halls E, F, & D 400 North High St. Columbus OH - Apr 25 - 27, 2017
Engineer 3D! Training + Technology Conference at Hyatt Regency Milwaukee 333 West Kilbourn Avenue Milwaukee WI - Apr 25 - 26, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering EDACafe - Electronic Design Automation GISCafe - Geographical Information Services TechJobsCafe - Technical Jobs and Resumes ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy Advertise