ADVISORY/SynTest's Presentation at EDA&T in Taiwan Covers How to Reduce Test Costs

  • (BUSINESS WIRE)--

    -0-

    Who
    SynTest Technologies, Inc., the leading supplier of DFT (Design
    for Test) tools and services for SOC (System On Chip) design, presents
    and exhibits at the Electronic Design & Automation Expo (EDA&T)
    (
    http://www.english.edatexpo.com/)
    
    What
    Presentation
    VirtualScan(TM): The best scan test reduction solution
    Hsin-Po Wang and Jacky Yeh, SynTest Technologies
    
    When/Where
    Presentation
    October 4, 2002
    1-1:50 p.m.
    Room 2
    
    Exhibit
    October 3-4, 2002
    9:30 a.m. - 5:30 p.m.
    
    Lakeshore Hotel
    No. 51, Lane 775, Ming Hu Rd.
    Hsinchu, Taiwan
    
    

    About SynTest

    SynTest Technologies, Inc. develops and markets advanced Design For Test (DFT) and Design For Debug/Diagnosis (DFD) tools to semiconductor companies, ASIC designers and test groups throughout the world. Headquartered in Sunnyvale, California, the company has offices in Taiwan, Korea and Japan. The company's products improve an electronic design's testability and fault coverage, and result in reduced defect levels, reduced costly tester time, and reduced slippage in time-to-market. These products include tools for built-in self-test (BIST) for logic and memory, boundary-scan synthesis, DFT testability analysis, scan synthesis, automatic test-program generation (ATPG), concurrent fault simulation, silicon debug and diagnosis. More information is available at www.syntest.com.

    SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408/720-9956, E-Mail: Email Contact.

    Notes to editors:

    VirtualScan is a trademark of SynTest Technologies, Inc.

    All other tradenames and trademarks are the property of their respective owners.

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    Acronyms:
    ASIC:          Application Specific Integrated Circuit
    BIST:          Built In Self-Test
    DFD:           Design for Debug/Diagnosis
    DFT:           Design for Test
    SOC            System On Chip
    
    


    Contact:
         ValleyPR for SynTest
         Georgia Marszalek, 650/345-7477
         
    Email Contact



  • Source: SynTest



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