Actel Enhances its Integrated Design Environment with Verific Design Automation Software

FPGA Design Tool Includes Language Capabilities through Verific

Alameda, Calif. -- November 15, 2007 -- Verific Design Automation today said that Actel Corporation (Nasdaq: ACTL) has integrated its Verilog and VHDL parsers, analyzers and elaborators to serve as the front end to the Libero™ Integrated Design Environment (IDE).

The recently introduced version of Actel's Libero IDE was enhanced to ease the system-level design process for all of its field-programmable gate arrays (FPGAs). Its SmartDesign design entry capability lets designers move to a higher level of abstraction, reducing FPGA design and development time, improving productivity and speeding time to market. Through a tight integration with Verific's front-end software, designers are able to create and automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components.

"Verific's goal to provide quality products and exceptional support is perfectly in tune with our way of thinking that keeps us innovating to ease design challenges," says Ken Joyner, director of engineering at Actel.

Verific's products, used in various Electronic Design Automation (EDA) tools for exploring, navigating, analyzing, documenting and modifying designs, include Verilog, SystemVerilog and VHDL parsers, analyzers and elaborators, as well as a register transfer level (RTL) database. All are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and come with online support and maintenance.

"The latest version of Actel's Libero IDE is a welcome tool for FPGA designers," remarks Rob Dekker, founder and president of Verific. "We're delighted that Actel selected us to work to improve and accelerate the design process."

About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: http://www.verific.com.


For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822
Email Contact

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.



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