EDAptability: 100% RTL @ Speed FPGA debugger - Groundbreaking technology opens new ways for signal visibility EDAptability announced the availability of its new “intelligent Built in Streamer (iBiS)”. The tool offers 100 % RTL signal visibility and at speed debugging, so you can have freely running clocks without the need to slow them down for debugging. No re-synthesis is needed for debugging and the initially implemented general debug structure has no impact on timing or on the combinatorial logic. Only one fraction of the design is post-simulated starting from a timepoint shortly before the bug or the timezone of interest, even if the test already runs for hours before. The signals with their original names and types can be viewed with EDAptability's VCD viewer or any other third party VCD viewer.
Apache Design Solutions and Optimal Corporation to Present Technical Webinar on IC-Package Co-Design for Power Integrity Apache Design Solutions announced that it will partner with Optimal Corporation, a leader in 3D power, signal and thermal integrity analysis for IC Package, System-in-Package (SiP) and PCB design, to present a free online technical webinar that will explore the symmetrical use of package-aware chip analysis and chip-aware package analysis to address true IC-Package co-design.
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