Process variability can have a dramatic effect on yield. This is especially true in the lithographic process where variability puts image fidelity at risk even when the operating conditions of the lithographic system (lithographic process window) are acceptable. To reduce the risk of silicon failure, avoid costly respins of both masks and silicon and safeguard time-to-market schedules, Calibre OPCverify detects lithographic errors or marginalities caused by process variability before the design goes to the mask or wafer manufacturer.
Calibre OPCverify, which uses silicon-proven simulation models from Calibre OPCpro, is the next generation of RET verification, providing high simulation coverage of the entire chip to ensure silicon-patterning success. The Calibre OPCverify pixel-based, dense simulation engine accounts for the effects of process variability using patented algorithms that define the conditions (dose, focus) that adversely impact pattern transfer. All Calibre OPCverify modeling capabilities have been thoroughly characterized for the most advanced process conditions in production, including immersion lithography. The rigorous model development and verification methodology used for the Calibre OPCverify tool allows it to satisfy the stringent requirements for both RET recipe validation and mask verification.
Another benefit of using Calibre OPCverify is that the tools take advantage of existing hardware in the most optimized way possible. With the combination of high-speed computing power available on today's workstations, and the concurrent processing functionality in Calibre MTflex, very fast turn around times for full-chip RET verification can be achieved. Because of the design-independent nature of the tool, users experience very predictable runtimes and excellent scalability. While actual run time is dependent on the hardware used, the Calibre OPCverify terapixel simulator is scalable to hundreds of CPU's, can handle flat or hierarchical data, and ensures predictable turn around times in a production environment.
"Verification of post-OPC output is critical to minimizing mask respins of million dollar mask sets, and avoiding time-to-market delays," said Hiroyuki Tsujikawa, Semiconductor Company, Matsushita Electric Industrial Co., Ltd. "Building on the Calibre platform for nanometer technologies has enabled Matsushita to develop a world-class process and gain a competitive advantage in delivering a wide range of System LSI."
"For 90nm and smaller technology nodes, the complexity of OPC and the constraints that go with it require verification to prevent silicon failures," said Joe Sawicki, vice president and general manager for the design-to-silicon division at Mentor Graphics. "Mentor is pleased to have Matsushita join the large and growing ranks of top semiconductor companies who have adopted our production proven verification platform."
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $725 million and employs approximately 4,050 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics and Calibre are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)
Mentor Graphics Carole Thurman, 503-685-4716 Email Contact or Sonia Harrison, 503-685-1165 Email Contact