Bluespec - ESL Synthesis

What is your strategy for doing that?
Shiv: My concise description is to focus on a few customers, make them successful and widely publicize those successes.

That takes time on both the sales and implementation side?
Yes. That is reflected in how much money you take in, how you calibrate your burn rate, how you set the size of the organization, how careful you are in terms of matching revenue and expenses and all those things. It is a philosophy. We consider this to be a marathon not a sprint. We have geared ourselves to running a marathon,

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Mentor Graphics Announces User2User 2006 Best Paper Award Winners User2User 2006 was held May 2 through May 5, 2006, in San Jose, California, and was attended by approximately 500 Mentor customers from 12 countries. U2U 2006 presentations and papers are available at

Cadence Debuts Industry's First Transaction-Based System Verification and Management Solution
Cadence announced the industry's first automated end-to-end transaction-based flow from architectural modeling to full system validation. The newly enhanced Incisive Enterprise solution combines verification management technology, SystemC/mixed-language simulation, and hardware acceleration/emulation for customers verifying and validating complex SoCs and systems. The Incisive Plan-to-Closure methodology has been updated to include transaction-based acceleration and transaction-level modeling methodologies to guide design and verification teams through the verification process.

Joe Costello to Keynote Monday Opening of Design Automation Conference; Former Cadence CEO Challenges Semiconductor Industry to See Technology Through the Eyes of Consumers
Joe Costello, chairman of Orb Networks and former CEO of Cadence Design Systems, will open this year's Design Automation Conference (DAC) with a keynote titled, "iPod or Iridium: Which One Are You Going To Be?" During this session, Joe will challenge participants with these fundamental questions: Are you going in the right direction? Are you bending your minds with the complexity of implementing modern-day systems and chips? Are you racing toward the right finish line? What are consumers really looking for? What will convergence really lead to and are you positioned to take advantage of all it will bring our industry and our world?

Mentor Graphics Introduces Catapult SL, the First High-Level Synthesis Tool to Create High-Performance Subsystems from Pure ANSI C++ Mentor today expanded the Catapult product line with Catapult SL (System Level). The Catapult SL tool supports complex hierarchical design, includes new technology that improves block-level performance and offers links to power analysis tools to help reduce power consumption by up to 30 percent. The Catapult SL tool is priced at $350,000, and is currently available in either term or perpetual licenses. Other members of the Catapult product family are priced starting at $140,000

National Semiconductor Equips All Employees With 30-Gigabyte Video Apple iPods to Cap Off Most Successful Year in Company's History While designed for personal entertainment, the popular Apple MP3 player will be used as a new training and communications tool at National, providing a convenient real-time method for its 8,500 employees to download National podcasts and other employee communications. National reported sales of $2.16 billion for fiscal 2006, which ended May 28, 2006

43rd Design Automation Conference Features Management Day Focused on Intersection of Business and Technology DAC will offer a Management Day track again this year, following the success of last year's "Management Day at DAC." The Management Day track, to be held on Tuesday, July 25, helps managers make decisions where the technology and business of IC and system design meet. The 43rd DAC will be held July 24-28, 2006, at the Moscone Center in San Francisco.

Other EDA News

Gidel is proud to introduce PROCSpark ll™

Design Automation Conference to Host 3rd UML for SoC Design Workshop July 23

Freescale Tapeout Marks 1,000th Design for Cadence CeltIC NDC

Making the Case: ENOVIA MatrixOne to Outline Criteria for Driving Corporate-Wide Buy-In for PLM

Comit Systems Expands Adoption of Cadence Encounter Digital IC Design Technology

Renesas Deploys Novas' Debug System

ATI Implements Mentor Graphics Modular TestKompress for Production Test of Advanced 90nm Graphics Processor

Verari Systems Announces New CEO

Making the Case: ENOVIA MatrixOne to Outline Criteria for Driving Corporate-Wide Buy-In for PLM

Celoxica, GiDEL Bring FPGA+DSP Acceleration to Embedded Imaging Applications

Altera's Stratix II FPGAs Provide Complete Design Security Solution for Protection of Intellectual Property

Hong Kong's ASTRI Reconfirms Cadence as Key EDA Solutions Provider

Other IP & SoC News

MIPS Technologies Joins The SPIRIT Consortium

Acacia Technologies Licenses Resource Scheduling Technology to Madrigal Soft Tools

Samsung to Benefit From ARM and National Semiconductor Power Management Collaboration

AnalogicTech Announces High Efficiency, Integrated Step-Down Converter, LDO for GSM Applications

Therma-Wave Wins Fab Expansion Repeat Metrology Orders

Darfon Selects Cypress's WirelessUSB(TM) LP Radio System-on-Chip and enCoRe(TM) II MCUs for Next-Generation Wireless Mice

Wave Systems Announces New Licensing Agreement with STMicroelectronics for Additional PC Security Software

Avago Technologies Introduces Higher-Resolution Reflective Optical Encoders with Increased Performance, Temperature Tolerance

LSI Extends 4 Gb/s Fibre Channel Reach With New Teradata Deployments

Imagination Technologies Formally Launches U.S. Operations

Primarion Introduces Industry's First Dual-Phase, Programmable Digital Power Conversion and Power Management IC

National Semiconductor's New Boomer Audio Subsystems with RF Suppression Help Shield High-Frequency Interference

DALSA Semiconductor Delivers World's First 100+ Million Pixel CCD Image Sensor Chip to Semiconductor Technologies Associates 'STA'

IDT Enhances Efficiency of Next-Generation Wireless Infrastructures with Industry's Only Pre-Processing Switch

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