Similar types of benefits. If you are trying to express concurrency, which you often are trying to do in testbenches, as well as if you are creating golden reference models that can be sued for verification comparison with an actual implementation being able to provide hardware accuracy, being able to get complexity done quickly is tremendously valuable. Finally, those who want to do designs or want to pass the designs, the benefits are obvious in terms of being able to synthesize no compromise RTL out of the design.
Synthesis extensions available today if you go on the website. You can download software documentation and examples that provide a language reference manual, tutorials, code examples, user guide. That is important in a free fashion for untimed simulation. A lot of the type of things people do today with SystemC based models. That works with standard tools that are available today.
ESE for untimed simulation, no clocks
ESEPro for clock scheduled simulation, available today
ESEComp will synthesize Verilog RTL from SystemC designs, demos at DAC
Rolling out in the second half of the year
Customer quotes from Deepchip and your responses on your website raise issues related to learning curve associated with new methodologies and/or tools.
Typically we have a three day training session. We go over slides, tutorials and so forth. All the quotes you have seen and in every evaluation we have done through design and verification has exceeded that 2X improvement for the first design out of the gate after one week of training and evaluation preparation you are productive. It takes some time to really become an expert and it takes some time to feel comfortable but productivity really happens from day one.
There is an interesting discussion of experience in the letter from the ST engineer that said “Even after coding with this for a few weeks I was convinced that I was more efficient with RTL. But then I started getting into the more complex part. It sort of became easier. In the end it looked like I was 2X faster. For my next design I much prefer to use Bluespec.”
So the first project is highly productive but there is a period of becoming comfortable, an adjustment to loving the tool.
In general we found when people get through their first project, they never want to go back to RTL level design.
Is this based on a double blind study or a gut feel?
Actually, a little bit of both. In many cases someone has done a similar block where they had comparative data. They are providing that comparison with their experience in the Bluespec projects. This is not in all cases because sometimes they are building a new block. Not an apples ot apples comparison. In the majority of cases there is some sort of apples to apples comparison in the company so they can provide feedback.
So, you are providing new tools or extensions of tools to a targeted end users rather than trying to change who does what?
I think that is true. As Shiv talked about the Bluespec SystemVerilog tool targeted hardware designers and architects familiar with hardware languages and concepts. With that solution we are replacing what they are doing today. With the SystemC product we are targeting people that are doing modeling, architecture and verification today with SystemC. We are providing an opportunity to add design to that mix. The main thing we are targeting is along the lines of what people are doing today but allowing them to do that significantly better. Over time that will provide some opportunity to do more. We believe very, much in fitting with existing methodologies and tool sets and not requiring firms to do a lot of organizational learning to adopt a really compelling solution. If you try to change too many dimensions it becomes very difficult to adopt a new approach.
How does Bluespec sell its products?
It's primarily direct sales. We have a few reps. We have a west coast presence that covers the east coast and east Asia. We have somebody how cover the other two thirds of the US and Canada. We have somebody who covers Europe and India. We have a few select reps that work in a direct sales capacity and a distribution rep in Taiwan.
How many seats does the ever hard to define typical user have?
It depends on the product. The synthesis tool is a time based license. Typically there would be some sharing. There will not be one tool at a customer. We have simulation based license as well. These depending on the customer could have multiple seats per engineer to less than one seat per engineer. It depends upon how the tool is leveraged by a particular engineer.
I think you said that the major application for these tools has been mobile cell phones.
It is mostly a coincidence rather than anything else. We have had tremendous success with mobile semiconductor and systems companies. There are some good reasons why that area of the market has adopted Bluespec. It offers the ability to provide very rapid architectural exploration and feedback. Not only improving the design cycle but also being able to make the best decisions about the implementation for consumer marketplace. Lots of good fits there. The tool sets are generally applicable to chip design whether ASIC or FPGA.
Whom do you see as competition for your products?
Generally we do not see a direct competitor. There are people currently using SystemVerilog. The decision would be do I do Verilog level or do I do it at a higher level. We see the algorithmic synthesis tools as being really very complementary to Bluespec. If you want to have an implementation generated automatically from a SystemC or C based implementation, that's a terrific solution for an algorithmic synthesis tool. If you are looking to do that algorithm by hand in RTL, we think we are a viable alternative to that. They automate high level descriptions from C to RTL. We focus on complex control logic and complex control. We expect that we will be within the same design groups as a complete ESL story for people doing hardware design.
What is the market size for this type of product?
If you think about the market size for people doing modeling and chip design today, that's the TAM (Total Available Market) for what we are doing. Our focus is on people looking to drastically improve and drastically reduce the cost of doing chip development whether ASIC or FPGA and for people to improve the quality and wrestle with the complexity of what designs have become today. Back when I did my first chip design, I worked on a MIPS processor at LSI Logic. My first design was done in schematic capture. You can't afford to do that with designs today given their complexity. It is getting to the point where it is untenable to do very high quality, fast implementations of designs in RTL. We are offering something the industry didn't have prior to Bluespec, which is a way to take complex hardware, complex concurrent based design and do them at a much higher level and higher quality and yet integrate nicely with existing RTL level tools.
When we go to prospects, they are making a decision to continue to do RTL level designs or not. In some sense our competition is existing approaches. But in terms of the technology and in terms of where we are positioned, the types of solutions we do well which is taking a high level description of complex data paths we are not aware of any competing technology.
What do you see as obstacles to your commercial success?
Shiv: Inertia is a big one. Methodology change is never easy. In addition to retraining people in a new skill set, there are always things people need to work through in terms of implications on process and methodology, organization and on who does what. These things take time. We are 15 years into RTL design. A lot of people have tried things and have a sour taste, a very jaded view about the possibility that there is something that can do a very high quality hardware implementation for the types of things they are doing. Part of the inertia is really overcoming preset viewpoints as to what is possible.