Bluespec - ESL Synthesis


What deficiencies and issues do you see with SystemC?
SystemC is used today to build high level functional models and do architectural exploration at that level where it is really detached from what the implementation will look like as well as what the hardware architecture and microarchitecture will look like. What this means is that when people move further into the design process when they get into implementation is that people do a manual rewrite because there is no automated way to go from those models into an efficient implementation. They typically get only one shot at doing that because they have to do it essentially by hand. There are obviously a couple of issues with it. You have to maintain two separate environments where there is not a lot of consistency in reuse across them. The other issue is that when you do this high level modeling you are really detached from understanding the implications of what your choices are in terms of the real hardware. Think about things like queuing performance you can understand at a high level model but understanding power, area and cost, all of those things, if you do that in an environment that is devoid of understanding what the hardware looks like then you really can not make accurate tradeoffs. Ideally, particularly today with the emphasis on mobility, creating optimal solutions for those types of markets really means solutions in terms of cost because you are dealing with the consumer market as well as low power and low energy usage because you are not running off the wall, you are running on batteries.

The other thing that we have seen is that the models for concurrency and communication inside of SystemC with threads and events is very much an RTL level kind of model for managing those things. Concurrency with threads is really very difficult. We have found with people whom we've talked to and who have build SystemC models is that they tend not to build a lot of concurrency because they are trying to avoid a lot of the complexity that threads and events forces upon them. This means that the models inherently are not going to reflect what the hardware is going to look like because you don't have a lot of concurrency in the model. It is difficult to scale complex concurrency based models. This means that ultimately it is avoided. Again it makes it harder to translate those high level models automatically or even manually into a real implementation.

Are you familiar with GartnerDataquest's ESL Landscape shown at DAC in 2005 that shows where vendors in high level modeling fit in terms of automating synthesis down into RTL? There are three different design types or methodologies: algorithmic, processor/memory and pure control logic based. The second I equate to complex data path design as in memory controller and DMA controllers. If you look at the firms that are automating high level ESL models, e.g. Forte, Accelchip, and Synplicity, they all squarely fit into the first category. These are people that are taking C and C++ kinds of descriptions of an algorithm, typically tightly nested for loops, and automating the generation of RTL. Those would be things like FIR filters and IFFTs. Everything else that people do in a typical hardware design doesn't fit into that category. So if you are building a cache controller, a DMA controller, a network engine, a bridge chip …, all of those things do not fit into that category. In terms of synthesis Bluespec with our SystemVerilog based product is the only solution that attacks and raises the level of abstraction as well as automating synthesis in those areas.

The question then is “What is not covered, previous to this announcement with existing SystemC, C and C++ synthesis?” Thierriy Baucheon, R&D Director at HEG Division of STMicroelectronics says “We've looked across the things that we are doing and Bluespec is the only solution that can address 90% of that.”

Based upon these issues with SystemC and where current products fit today we believe that one of the big things needed with SystemC is ESL synthesis as described by GartnerDataquest Landscape.

Where does Bluespec stand?
We had our initial customer in Q2 of last year and an uptake including three of the top IDMs in the mobile industry. Our results are proven and pretty compelling quote saying we are twice as fast for the first project out the gate with them.

Bluespec has been used for cache controllers, processors, memory controllers, DSPs, bus bridges, DMA controllers, serial controllers, audio, video, bus controllers all of those things which you would never see a traditional behavioral synthesis tool do but which is something we can do with ESL Synthesis much more effectively and yet still generate high quality RTL.

The product?
Shiv talked about the level of abstraction for the way concurrency is expressed in communication. Basically we have this concept that instead of threads and events we have something called rules which allow a much higher level way of describing things closer to the operation that helps simplify the complexity of expressing concurrency. Then there is something called interface methods which allow a much more powerful way of expressing how you communicate between blocks. Rules are the sort of how you express within a module, how you articulate complex currency. Then interface methods are how you compose larger systems very quickly. You can start thinking about building a harness of what your interfaces look across your system. The power of the interface method is the ability to in essence express not only the what the port list looks like or what the wire interface of the port looks like but as well what the correct protocol and behavior is for communicating between blocks. That becomes a very powerful way of taking building blocks and composing them together much quicker without having to resort to paper specification on what the interface looks like. In a sort of automated way get interfaces properly connected and working. Both of these things are built into our ESL extensions with SystemC. We have a language reference manual as well as examples and tools available on our website for download.

What is the tool flow for your product?
You can think about a system model where you may take arbitrary SystemC block as model say a codec model and mix them up with other components in you system that are designed with ESL synthesis extensions which we area calling ESE (easy). Then you can simulate those in standard SystemC and C tools (GCC, the OSCI simulator or a commercial SystemC simulator). The arbitrary sort of SystemC blocks you have today would run through the core SystemC with TLM extensions and the ESE based design would run through the ESL Synthesis extensions. The whole design will simulate. Later this year we will be rolling out our synthesis tool, ESEComp that will take the ESE SystemC blocks and synthesize very high quality RTL out of them.

What are the benefits?
What are the things that one would like to see out of an ESL solution for chip based design? Common environment, common language, unified environment for doing modeling and verification. Not only very high level macro architectural exploration but also marry that with effective micro architectural exploration, particularly as you start thinking about low power and low cost design fro consumer based solutions. Ideally in addition to algorithmic synthesis, solutions that are commonly available, you would like to be able to synthesize all aspects of the design including the complex data paths and control logic.

What does ESE provide for modeling and architecture?
For people doing SystemC today it certainly provides a single environment for model design, eliminates the need for separate environment, provides the opportunity for a complete different implementation, provides a common language for modeling and architecture people to discuss things with design people. It is more accurate with respect to the hardware. You can really assess the implications of your choices in terms of power, latency and timing. It provides much faster implementation of complex concurrency and design composition through the interface method than you would have with threads and events and a strict RTL model for communicating between blocks.

What does ESE provide for verifications?

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