EDA Week in Review

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And Celestry Design Technologies, provider of physical analysis software and services, said STMicroelectronics has selected Celestry's Hot-Carrier Injection (HCI) analysis products to increase the performance of ST's high-end designs.

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Centillium Communications said Artisan Component's industry-standard library products were used in its Entropia and CopperFlite families of products. Centillium's design challenge was to develop high-density products utilizing TSMC's 0.18-micron low-voltage process. Artisan provided its TSMC process-optimized memory generators and SAGE-X Standard Cell Library. With Artisan's libraries integrated into Centillium's Entropia and CopperFlite products, Centillium said it could provide innovative products optimized for speed and density to its customers.

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Cadence Design Systems announced a new NC-Sim Plus package that provides an integrated front-end logic design solution. NC-Sim Plus includes the Cadence NC-Sim mixed language simulator, TestBuilder open-source testbench development tool, Verification Cockpit functional verification tool, and the BuildGates synthesis tool.

"In this era of multi-million gate ASICs, reusable IP, and SoC designs, verification has become the major bottleneck in getting designs released," said Rahul Razdan, corporate vice president and general manager of Systems and Functional Verification at Cadence, in the company's announcement. "It is a real challenge for engineers to know when a design has been verified and meets specified implementation criteria. Our unique solution combines the tools required to provide reliable answers to today's verification-through-implementation challenges."

Cadence said NC-Sim Plus directly addresses the key challenge that verification engineers face: the lack of a reliable means to confirm that their design has been fully verified. Without this information, designers are often caught in a cycle of design respins that are costly and time-consuming. NC-Sim Plus brings together the tools that give engineers the confidence that their designs have been fully verified.

At the center of this new product bundle is NC-Sim, the mixed-language simulator. It was designed to handle the most complex ASIC, SoC, and FPGA designs. The open-source TestBuilder testbench development tool provides the first step in creating a transaction-based verification environment. It is based on the familiar C++ language and includes a set of C++ class libraries with the transaction models and functions designers need.

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Also from Cadence comes an upgrade to its Signal Processing Worksystem (SPW), a system-level, hierarchical block diagram design solution with an optimized flow for implementation that aims to help manage the complexity of today's communications and multimedia designs by giving hardware, software, and RF engineers a means to collaborate on their projects, which can significantly reduce design time and risk.

The new version of SPW, version 4.8, incorporates new capabilities and enhancements to both the core system and its links with other tools, including tight integrations with the Xilinx Coregen solution, with the analog design flow that supports the Cadence AMS Designer, and with SystemC 2.0. SPW 4.8 users can enter and simulate designs consisting of various types of models including C, C++, Verilog, VHDL, Verilog-AMS, SystemC, ISS, and Matlab. SPW 4.8 also supports server farms on HP-UX, Solaris, and Linux platforms to accelerate bit error rate (BER) simulations studies.

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People On The Move
0-In Design Automation Inc. announced the promotion of Dr. Emil Girczyc to president and CEO. 0-In co-founder and former CEO Dr. L. Curtis Widdoes has been named chief technology officer and remains chairman of the board of directors.

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For more announcements from this week, please click here.

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