Lead-free wafer bumping and electronic packaging are emerging as an effective means of creating better performance semiconductor devices and gaining a competitive edge in a crowded market.
This constant innovation is furthered by growing environmental concerns from authorities such as the European Union's Restriction of the Use of Hazardous Substances' (ROHS) Directive on hazardous materials. End-user demand for technically superior low-cost products, fuelled by the influx of Southeast Asian companies, is also prompting European participants to step up innovation.
Participants utilise lead free alternatives such as the tin-silver-copper (Sn-Ag-Cu) also called as SAC system combined with materials such as gold. However, the slow adoption of these processes is due to issues such as high yield loss and low reliability.
"For instance, flip-chip (FC) assembly qualifies for eutectic PbSn (lead-tin), but proves to be difficult for lead-free material," explains Frost & Sullivan Research Analyst Sivakumar Muthuramalingam. "High yield losses occur after the board assembly due to substrate warpage."
The high fatigue characteristic of lead free alloys results in temperature challenges causing flux problems, which can adversely impact manufacturing processes.
"The integration of lead-free materials into FC/chip scale package (CSP) applications is difficult due to the material characteristics such as stiffness, and material compliance that increasingly makes reliability an issue," points out Mr. Muthuramalingam. "To overcome this, researchers in Germany are continuously working to develop novel wafer bumping technologies for a wide range of applications."
Constant innovation and enhanced products such as electroless nickel bump, stencil printing and electroplating will also help in solving issues surrounding the lack of standardisation in the packaging industry, especially since several designs are utilised for the same package.
While the European electronic packaging market leads in terms of research and development - backed by leading microelectronic research institutes such as Institut fur Zuverlassigkeit/Mikrointegration (IZM Fraunhofer (Germany)) - it is facing a problem of underfinancing and stiff competition from the Far East.
Southeast participants are intensifying competition as the packaging service providers in Europe are unable to continue to support the drive for increasingly lower price margins.
"For instance, Netpack-Europe.org, the official organisation for chip packaging manufacturers in the European Union, is likely to be closed during the year due to lack of financial support," observes Mr. Muthuramalingam. "To combat this issue, packaging service providers must develop and implement a fiercely aggressive market strategy with respect to price, customer service, quality and reliability."
Going forward, greater standardisation of electronic packaging technologies, race towards miniaturisation of electronic devices and rise in demand for consumer electronics will sustain end-user interest in next-generation back-end semiconductor manufacturing technologies.
World Back-end Semiconductor Manufacturing Technologies is a part of the Electronics vertical subscription service, and provides an in-depth analysis of the latest trends in back-end semiconductor manufacturing technologies. It also looks at the future size and structure of the back-end contract manufacturing industry. The research service also analyses the key technology drivers, and evaluates the challenges that must be overcome for each novel back-end semiconductor manufacturing technology to realise its potential. This vital information will allow participants to effectively plan for the long term and identify and maximise all opportunities for growth. Executive summaries and interviews are available to the press.
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Keywords in this release: back-end semiconductor manufacturing technologies, European Union, Restriction of Hazardous Substances, RoHS, tin-silver-copper, Sn-Ag-Cu, SAC system, gold, copper, high yield loss, flip-chip, FC, Germany, PbSn, lead-tin, board assembly, underfill, substrate warpage, thermal mismatch, reflow, eutectic tin lead solder, flip chip/chip scale package, FC/CSP, Institut fur Zuverlassigkeit/Mikrointegration, IZM Fraunhofer, IMEC, Belgium, Netpack-Europe.org
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