Power analysis has been added to the post-placement analysis suite and is activity based, using data from SAIF files generated during simulation. The analysis detects power issues early for power-grid design planning and IR drop analysis. Chip2Nite 2.3 will also generate custom wire-load models based on physical properties of the design for more accurate timing prediction during the synthesis process. Finally, predictive floorplanning delivers physical information, such as pin locations, for early detection and identification of critical design issues.
"Design planning, placement and analysis are not just a good thing for logic designers to have as feature sizes shrink below 130 nanometers, they are crucial to design closure," said Michael Naum, president and CTO of Silicon Dimensions. "Attacking problems on the front end eliminates iterations back and forth between the logical and physical designers and ensures right-first-time design."
The new power-analysis capabilities will allow designs to identify local areas of high power consumption, before physical design begins. With this information, designers can either try correct the design issues causing the local hot spots, or plan early for the increased power consumption needs of those areas design. The early detection of these issues will save weeks of design time by avoiding the design iterations that typically happen as designers try to correct these issues later in the design process.
Utilizing the early analysis capabilities of the Chip2Nite platform, designers now will be able to generate custom wire-load models for their design be rapidly modeling the interconnect of the design. Traditional wire-load models have become inaccurate as design geometries have shrunk. Chip2Nite’s rapid analysis can quickly produce custom models for the design, which then can be fed into traditional synthesis tools, greatly improving the quality and accuracy of the synthesis runs.
Early block level floorplanning analysis is limited by the availability of block pin assignments. Chip2Nite’s new physically aware, pin-assignment algorithm allows designers to quickly determine a seed placement to begin floorplan analysis. This assignment can later be refined as the design progresses. By allowing the designers to quickly determine a seed pin assignment, weeks of design time can be saved as designers can eliminate the trial and error that they typically go through determining early pin assignments.
Better communication, leveraging investment
The Chip2Nite platform directly addresses the difficulties encountered in current methodologies by enabling logic design engineers to contribute to design closure early in the development process. By providing the logic designer with the ability to perform early design planning, logic designers can now understand the affects that their decisions have on the entire chip implementation process. By allowing logic designers to Get It Right the First Time, needless and costly iterations are removed from the design process.
Floor planning, placement and optimization tools from Cadence, Synopsys and Magma are not aimed at logic designers. Chip2Nite is specifically designed to provide physical information for logic designers needs and works with standard formats, including Verilog and Design Exchange Format (DEF). The Chip2Nite early design planning platform includes design and constraint analysis, floorplanning, placement, post placement analysis, and optimization capabilities.