CST to exhibit at DesignCon and hold Tutorial Sessions

Each year, engineers from around the world flock to DesignCon, an educational conference for chip, board and systems design. The conference is known for its in-depth program of technical sessions, aimed to enlighten attendees with the latest theories, methodologies, applications and design tools. CST will be heading to the show and exhibiting at booth #109 from January 29-30 in the Santa Clara Convention Center. 

Not only will we be at the exhibition, but we also wanted to take the opportunity to discuss electronic package design and PCB-package co-simulation in the technical track covering signal integrity (SI) using electromagnetic (EM) analysis techniques. 

Our tutorial sessions include:

Accurate Modeling of Electronic Package Designs: Hybrid vs. 3D EM Full Wave Solvers 
Date: Tuesday, January 28
Time:  1:30pm- 4:30pm
Location: Ballroom K
Speakers: Antonio Ciccomancini Scogna (CST), Darryl Kostka (CST), Frank Paglia (Freescale Semiconductor, Inc.)

System Level Modeling Methodologies for PCB-Package Co-Simulation & Co-Design 
Date: Tuesday, January 28
Time:  1:30pm- 4:30pm
Location: Ballroom K
Speakers: Chiang Chun Tong (CST), Antonio Ciccomancini Scogna (CST), Linus Lau (CST), LianKheng Teoh (eASIC)

Apart from our participation in the technical program, a number of CST staff will be at the booth to facilitate demos of CST STUDIO SUITE® and discuss the use of electromagnetic simulation within the EDA workflow. Drop by and say hello at booth #109!




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