Samsung Delivers Strong 14nm FinFET Logic Process and Design Infrastructure for Advanced Mobile SoC Customers

Dr. Dipesh Patel
Vice President and General Manager, Physical IP Division
ARM

Cadence

“Our leading-edge customers see the performance and low-power advantages of 14nm FinFET design, and they’ve asked us to help them get there ASAP. The Cadence end-to-end design flow including signoff enables engineers working along the cutting edge to bring the benefits of 14nm FinFET design to the mobile and server markets.”
Dr. Chi-Ping Hsu
Senior Vice President, Research and Development, Silicon Realization Group
Cadence

Mentor Graphics

“Mentor and Samsung continue to be committed to providing the most advanced solutions for our mutual customers in both semiconductor process technology, and the associated ecosystem required to leverage new offerings like FinFET transistors. Mentor has always driven its technology development in partnership with key customers. Our collaboration with Samsung is yielding results that designers can access immediately.”
Joseph Sawicki
Vice President and General Manager, Design to Silicon Division
Mentor Graphics

Synopsys

"Our successful 14nm FinFET tapeouts with Samsung represent a major milestone in the multi-year collaboration between Samsung and Synopsys to deliver optimized FinFET-ready EDA tool and IP enablement for the node."
John Chilton
Sr Vice President, Marketing & Strategic Development
Synopsys



Contact:

Samsung Semiconductor Inc
Lisa Warren-Plungy, 408-544-5377
Email Contact



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