The EDA & MCAD/MCAE Almanac – Nominal Q2 2012

While many of us associate John with Michigan and the University of Michigan, he’s originally from Silver Spring, MD, a suburb of Washington, D.C. “I went to college at University of Michigan for 11 years, so it’s fair to say I’m from Michigan, too.”

His fondness of the University of Michigan and Ann Arbor is strong. He met his wife in college and his daughter Anne was born in Michigan. “I still go back to there to play in the alumni Marching Band at homecoming,” noted John. A fine trombone player since he was a teenager, he has also performed with the Peninsula Symphony for 25 years.

We talked as was getting ready to leave on a vacation at the Maryland home he owns, a home that has been in his family for many years. It sits on the beach of the Chesapeake Bay, giving him ample opportunity to sail his Sunfish sailboat off the beach or take the wooden kayak he and his wife built several years ago.

Yes, a wooden kayak. John recalled finding a company that sells kits for building wooden boats. Over the course of two summers, two weeks at a time, they built a kayak now housed at Chesapeake Bay. He said, with characteristic modesty, that the experience was like any other woodworking project, which meant following directions. It was straightforward, though he recalled lots of sanding. And definitely a bit of patience and fortitude.

The Wooden Kayak

Merging Chronology and CynApps

The 2001 merger of CynApps and Chronology created an interesting dilemma and one that was debated all the way to the board room. The question was how to make Forte Design Systems both a verification company and a synthesis company. Chronology was making money as a verification provider, but was not doing as well as Verisity (now part of Cadence).

CynApps was making a little money in the synthesis area, though not enough to pay all the bills; however, it was able to secure funding to grow the company. The decision was made to continue to focus on high-level synthesis and to utilize the plethora of verification tools to build a high-level synthesis environment with verification at its core.

And in that same year, Sony, Ricoh and Fujitsu became high-level synthesis customers of the newly combined Forte and the push was on.

Moving to a high-level synthesis business model was practical. Cynthesizer, Forte’s high-level synthesis software, was gaining traction, though Brett Cline said that the first few years of the merger were killers as Forte honed down at least five products into essentially just one with add-on capabilities. (Chronology’s TimingDesigner was still around in a separate division and ultimately sold to EMA Design Automation in 2007.)

Asia adopted a high-level synthesis methodology ahead of other world regions, willingly making a huge investment in a methodology shift. John, Sean and Brett all credit this turning point to the large number of consumer electronics companies. The high-level synthesis trend started in Japan because consumer device designs were a natural fit for this kind of software. High-level synthesis can implement image-manipulation algorithms, for example, into hardware. Japanese hardware engineers saw high-level synthesis as a way to stay ahead of the design curve from challengers in Korea and China. Moving up the abstraction level and adopting SystemC was a way to leapfrog ahead.

Brett acknowledged a few key and savvy individuals who led this methodology shift, many of whom are still in the business.

At this point in our interview, Brett opened up a spreadsheet and noted that Japan accounted for 99% of 2004 HLS revenue. Over time, it’s become about half of Forte’s revenue and still remains a large and important region.

United States, Korea and Japan, in particular, are design centers where Cynthesizer is in use for all kinds of applications. The USA is Forte’s fastest growing region, designing everything from custom processors to wired and wireless communication devices.

As we’ve seen in this profile, acquisitions have been good for Forte and it did another in 2009. It acquired Arithmatica to complement its product offerings with a portfolio of IP and datapath synthesis technology that has been integrated directly into Forte’s Cynthesizer product.

A look at a typical Cynthesizer design flow

Today, Cynthesizer is chosen primarily by design teams that want to reduce time-to-market pressures by designing at a higher level of abstraction and who require substantial improvements in circuit size and power. In many cases, teams create designs that would be impossible using RTL with their given resources.

The long-term benefit is generally not well understood. The value of SystemC-based IP and the ease at which it can be retargeted and reused is at the beginning of a project, are some things Verilog RTL has never achieved.

A Long Trek for Forte

“It’s been a long trek, in terms of finding the right set of customers who need a flexible format for IP reuse for the future,” said CEO Sean Dart. “Getting a product to that point was much harder than we expected. In 2000-2001, we never expected it to be this difficult. People shrug their shoulders and say, what’s so hard about a translator with clock cycles, far under-estimating what’s involved. The high-level synthesis tool needs to be able to handle different kinds of design styles, implementation methods and coding styles. It must be able to work with all of the downstream tools and libraries. It’s hundreds of things. Everybody underestimates the project.”

Many designers still hand code RTL for most of their designs, even now. Sean noted there’s a bit of inertia in the designer world, and Brett agreed. After all, any new change in the design flow can create more problems. For a designer, it introduces something new –– risk. They need to write in another language at another level of abstraction and change from what has been comfortable for them. “For a company like Forte, we need to prove we can make people successful and show a flexible format for reusing IP where a designer can get great results,” remarked Sean.

And, it finally happened with Cynthesizer. “We created a groundswell of support,” Sean stated, with Brett nodding his head in agreement. “Designers came to understand the utility. Otherwise, their product will miss the time-to-market window. IP development is so much shorter. Once people have the experience, then a second experience, that’s when the groundswell happened.”

He continued: “IP must be compatible and it should be automatically implementable. It’s a key selling point for us. There are reasons to buy the first time and a reason for change. Design teams don’t go into high-level synthesis for IP that will give them two or three times performance. However, as process geometries get smaller, fully timed RTL IP may not be reusable. That’s where high-level synthesis can make a difference.”

At this point, Sean became even more animated and noted: “High-level synthesis offers a way for designs to be retargetable for the next level and an optimal solution for technology, speed and longevity of the design. A key selling point for Cynthesizer is that the IP can be used on another project with almost zero effort.” Forte estimates that while the productivity gain on first development of an HLS-based IP may be five-10X, reusing that IP block next time around yields over 25X.

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