"The EDA360 vision calls on key industry players to work collaboratively to solve growing design complexity challenges," said Dave Desharnais, group director, product marketing, Silicon Realization at Cadence. "Our close relationship with TSMC enables us to pioneer AMS, ESL, 3D-IC and DFM solutions that are critical to the productivity and predictability of SoC design at advanced nodes. Together, we ensure customers can accelerate their 28-nm designs and successfully get them into high-volume production."
"Our new reference flows reflect significant technological advances that result from close collaboration with industry leaders like Cadence," said Suk Lee, director of Design Infrastructure Marketing at TSMC. "The combination of Cadence end-to-end solutions with our new design methodologies ensures that designers can further accelerate the development of 28-nanometer designs."
TSMC and Cadence have collaborated in the areas of electronic system level (ESL), 3D-IC implementation, design for manufacturing (DFM), and analog mixed-signal (AMS) design.
Advanced ESL Capabilities Enabled by Cadence System Development Suite
The ESL capabilities, delivered as part of TSMC Reference Flow 12, are developed by Cadence and enabled by the Cadence System Development Suite announced last month. The suite features four connected platforms that enable hardware-software co-design from architectural-level development through to prototyping.
The combination of the TSMC Reference Flow 12 with the Cadence System Development Suite uniquely supports SoC virtual prototyping for TLM and TLM/RTL platforms, early software development using the open SystemC language, and advanced functional verification. In addition, the reference flow scales to support 28-nm development with a link to the TSMC iPPA power estimation tool, giving users the ability to better estimate the overall power consumption of their system and make early architectural decisions to optimize power.
Automated 3D-IC/TSV Design-for-test Support
Reference Flow 12 also leverages new technology developed by Cadence and imec, a world-leading nanoelectronics research institute based in Belgium, to automate production testing of 3D stacked ICs and through-silicon vias (TSVs). This new 3D-IC technology extends the conventional 2D ICs design-for-test (DFT) infrastructure to support dedicated 3D-focused DFT architectures, enabling pre-bond die testing and modular post-bond die and TSV-based interconnect testing, as well as final testing after packaging.
Additional Cadence contributions to the flow include 3D-IC support for a digital implementation flow, with static timing analysis, IR analysis, and thermal analysis, along with RC extraction and physical verification production flows.
Extending Support for Advanced Analog and Mixed-signal Designs
Cadence and TSMC have continued working closely together to add circuit optimization, sensitivity analysis for layout dependent effects (LDE), LDE-aware layout, device reliability analysis and multi-technology simulation (MTS) to the AMS reference flow to produce AMS Reference Flow 2.0.
Utilizing the Cadence Virtuoso unified custom/analog flow and its integrated Virtuoso® Spectre® Circuit Simulator, the AMS flow automatically identifies the devices and parameters that will most impact design performance and reliability by detecting issues like voltage overstress conditions, while guiding a connectivity- and constraints-driven layout. In addition, Spectre simulator's multi-technology-simulation (MTS) capability is used to verify integration strategy in which analog and digital die are integrated together.
In-design DFM Capabilities
Cadence has provided technology for high-speed pattern matching to identify multi-layer yield detractor patterns or hotspots. The pattern matching is part of the in-design DFM capabilities of the Encounter® Digital Implementation System and Virtuoso implementation technology. Each system's router can automatically identify and remove bad patterns. The Virtuoso in-design DFM capability also provides designers the ability to analyze LDE at the circuit level. As a means to ensure best quality of silicon and highest yields, TSMC has recently partnered with Cadence to offer DFM services to its customers at 40 and 28 nanometers.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
Cadence, Virtuoso, Spectre, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
For more information, please contact: Dean Solov Cadence Design Systems, Inc. 408-944-7226 Email Contact