Targeting Functions Included
AUSTIN, Texas — (BUSINESS WIRE) — May 11, 2011 — The Silicon Integration Initiative (Si2) announced today that the members of its Design for Manufacturability Coalition (DFMC) have unanimously approved the release of the OpenDFM 1.1 standard, an upgrade to version 1.0 which was released in 11/2010. This is an open, high-level DRC language that can generate popular verification languages with no loss of accuracy or performance. OpenDFM describes verification intent for leading process nodes, including conditional rules and ranges of acceptable values. It leverages a plug-in architecture to automatically generate output decks. Advanced DFM checks are supported by utilizing DFM parameters and attributes defined by the DFMC members. This new version includes:
- ESD (Electro Static Discharge) and Latch Up Checks
- A complete set Edge Operations and Edge Checks
- New Targeting Functions: Targeting functions bridge the gap between a layout style that allows only a few, very restricted layout patterns and a style with purely arbitrary layouts. Targeting functions transform database shapes, regardless of their origin and design style, into the on-silicon target shapes that design and manufacturing agree are the reference shapes for silicon.
- Implementations and qualifications by multiple DRC engines
“We are encouraged by the increasing momentum of the DFMC,” says Mark Mason, director for Design Data Integration at Texas Instruments. "Our beta tests of OpenDFM v1.1 have been successful across multiple EDA supplier platforms, and we are already seeing return on our investment in the OpenDFM standard in the form of interoperability and reuse.” TI reports that they are planning to use OpenDFM’s DRC standard as the baseline for several of their production flows. “We are currently moving our entire 28 nm Wireless platform DRC infrastructure to the OpenDFM standard, and plan to use it at 20 nm as well,” Mason said. “OpenDFM is already paying off for TI and we hope others will follow soon.”
“Physical verification complexity becomes multifaceted with the move to advanced process nodes. Both the EDA industry and its customers must understand and respond to these challenges,” says Ken Potts, director of marketing, Silicon Realization, at Cadence Design Systems. “Cadence implemented OpenDFM rules on its Physical Verification System, a key Silicon Realization technology. The product combines analog and digital IP and Si2 OpenDFM rules to optimize the increasingly important interface between verification and manufacturing.”
The OpenDFM 1.1 standard, which is being made immediately available to the public at no charge, can be obtained at this link: https://www.si2.org/openeda.si2.org/project/showfiles.php?group_id=68. Members of the DFMC also have access to substantial adoption collateral, such as the OpenDFM parser source code, contributed test cases, tutorials, demonstration code, and more. To access this adoption collateral and to participate in the next phase of OpenDFM enhancements, please join the DFMC members; see this link for more information: http://www.si2.org/?page=491.
To hear more about Si2 project details, accomplishments, and work-in-progress, all are invited to attend the Annual Si2 Open Reception to be held on June 6 in San Diego, CA at the Design Automation Conference. Detailed information can be found here: http://www.dac.com/additional+meetings.aspx?event=56&topic=13. The OpenPDK and DFMC Coalitions are also sponsoring a workshop at DAC which will describe the common standards being developed between the two groups; see this link for more detail: http://www.dac.com/workshops+_+colocated+events.aspx?event=47&topic=3.
About the Design For Manufacturability Coalition (DFMC)
DFMC’s charter is to specify open standards for software interfaces between EDA software tools and manufacturing software. The specification includes standard terminology definitions, semantics and exchange formats for relevant manufacturing information. It also includes standard software application program interfaces (API) for models describing different manufacturing processes, yield mechanisms and circuit behaviors. Member companies include: Cadence Design Systems (NASDAQ: CDNS), GlobalFoundries, IBM (NYSE: IBM), Intel Corporation (NASDAQ: INTC), LSI (NYSE: LSI), Magma Design Automation (NASDAQ: LAVA) , Mentor Graphics (NASDAQ: MENT), Polyteda, Samsung Electronics (KSE:005930), STARC, STMicroelectronics (NSYE: STM), Synopsys (NASDAQ: SNPS), Tela Innovations, Inc., and Texas Instruments (NYSE: TXN).
Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 23rd year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world. See www.si2.org
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