PLDA and Aldec Announce PCI Express® DMA IP Supporting Advanced Verification Tools for FPGA Development

PLDA’s EZDMA IP and Aldec’s Riviera-PRO and Active-HDL tools enable ease-of-design and robust verification into design environments

SAN JOSE, Calif. & HENDERSON, Nev. — (BUSINESS WIRE) — April 28, 2011 — PLDA, the industry leader in PCI Express®, USB 3.0 and high speed interconnect IP, and Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for FPGA and ASIC designs, today announced the immediate availability of PLDA’s EZDMA IP solution, supporting Aldec’s Riviera-PRO for Linux and Active-HDL for Windows. Integrating Aldec’s advanced design verification tools with PLDA’s easy-to-use, yet powerful multi-channel DMA engine for the PCIe interface provides FPGA designers with robust validation capabilities. The PLDA EZDMA solution optimized for Aldec’s tools is available now for PCI Express® Gen1 and Gen2 designs.

The PLDA EZDMA package supporting Aldec’s Riviera-PRO and Active-HDL tools includes:

  • IP Core in synthesizable Verilog and VHDL RTL encrypted or clear source code
  • Complete, pre-compiled Riviera-PRO and Active-HDL library
  • Simulation script for both Riviera-PRO and Active-HDL
  • Full featured PCIe® testbench
  • Software Development Kit including a PCIe® software driver
  • End-point reference design

About Aldec's Active-HDL™ and Riviera-PRO™:

Active-HDL and Riviera-PRO are high-performance, mixed language RTL and gate-level simulators for ASIC and FPGA designs. They provide efficient design entry tools as well as tools for advanced debugging and analysis, including code coverage. These tools support industry standard languages such as VHDL, Verilog®, SystemVerilog and SystemC/C/C++. Top features include enhanced waveform viewer, seamlessly integrated debugging tools and the highest level of support for verification methodologies.


The PLDA EZDMA products provide a higher performance DMA solution than SoC based DMA engines and feature a vendor-agnostic user interface, allowing seamless device migration. The IP is configurable for resource optimization and customizable to fit specific customer requirements. Additionally, the EZDMA IP is hardware-proven and deployed in over 400 designs.

“PLDA’s proven reputation as a leader in the PCIe® IP market provides a great deal of value for Aldec’s established base of chip and SoC designers,” said Christina Toole, Marketing Manager for Aldec, Inc. “This integration with our tools provide a complete solution for designers who absolutely require first-pass silicon success.”

“The Aldec suite of products provides a set of extremely robust solutions for EDA verification,” said Stephane Hauradou, CTO for PLDA . “Like PLDA, Aldec places customer support as a foremost goal, ensuring that their customers get the reliable modeling they need to achieve their design goals.”

About PLDA

PLDA designs and sells a wide range of ASIC and FPGA interconnect solutions including bus controllers and SoC IP. The company offers complete solutions, including semiconductor IP, hardware, software, and design services. Founded in 1996, PLDA is privately owned. The company maintains offices in San Jose, California and headquarters in France and has a strong international distribution network. For additional information about PLDA, please visit

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. For additional information about Aldec, please visit


All registered trademarks and other trademarks belong to their respective owners.


Sabah Gaci
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Christina Toole
Aldec, Inc.
Email Contact

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