SEMATECH Announces 2011 Knowledge Series Line Up

Public forums aimed at forging consensus and driving solutions on critical industry challenges

ALBANY, N.Y. — (BUSINESS WIRE) — February 8, 2011 — SEMATECH today announced the content of its 2011 SEMATECH Knowledge Series (SKS), a variety of public industry meetings designed to enhance global knowledge and collaboration in key areas of nanoelectronics R&D by providing technology-rich forums to explore critical issues and build industry consensus.

“Our diverse meetings share a common purpose: to keep the industry moving profitably forward by making the most informed, cost-effective decisions possible,” said Dan Armbrust, president and CEO of SEMATECH. “It is more important than ever for our industry to come together, share ideas, build consensus, and drive actionable solutions. We believe we do that best with our SKS series.”

Hosted by SEMATECH and ISMI, this year’s worldwide conferences, symposia, and workshops will focus on the critical challenges and technology developments in next-generation lithography, materials and methods to enhance transistor and back-end development, and ways to improve manufacturing efficiency and yield.

The 2011 SKS meetings include the following, grouped by technology focus.

Lithography

  • Advanced Mask Cleaning Workshop, Sept. in Monterey, CA

Held in conjunction with the BACUS conference, the full-day workshop provides a forum for SEMATECH members, mask and wafer cleaning suppliers, and researchers to discuss advancements in technologies and solutions applicable to advanced mask cleaning and surface preparation challenges. Topics include sub-30 nm particle removal, molecular contamination removal, mask inspection defect analysis, and environmental approaches to mask cleaning.

  • International Symposium on Extreme Ultraviolet Lithography, Oct. 17-19 in Miami, FL

The EUVL Symposium, hosted by SEMATECH, Selete, EUVA, and IMEC is part of SEMATECH’s ongoing commitment to help mature the technology and infrastructure for extreme ultraviolet lithography (EUVL), including sources, masks, optics, resists, contamination control, and metrology to support EUVL pilot line manufacturing requirements.

  • International Symposium on Lithography Extensions, Oct. 20-21 in Miami, FL

The Immersion Extensions Symposium, hosted by SEMATECH in collaboration with IMEC and Selete and co-located with the EUVL Symposium, focuses on efforts to extend lithographic patterning beyond the 15 nm half-pitch node. Its primary emphasis is on patterning processes, emerging technologies, and techniques for improving process control.

Advanced Technologies

  • Surface Preparation and Cleaning Conference, March 21-23 in Austin, TX

This conference, which brings together the leading researchers from the semiconductor industry and the university community, addresses advanced wafer and mask cleaning and surface preparation technologies. Speakers and participants will explore current developments and ITRS challenges in wafer and mask cleaning, including wafer front-end, wafer back-end, advanced mask, and environment, safety and, health issues for the 32 nm node and beyond.

  • Design for Reliability Workshop - Stress Management for 3D ICs Using Through Silicon Vias, Mar. 17 in Santa Clara, CA

This workshop will bring together representatives from device manufacturers, electronic design automation suppliers, semiconductor assembly and test service providers, and the R&D community to explore mechanical stress-driven failure mechanisms, their associated test vehicles, and the characterization and modeling methodologies pertaining to via-middle through-silicon via 3D stacking technologies.

  • Workshop on Metrology for 3D Interconnect, July 13 in San Francisco, CA

Held in conjunction with SEMICON West, this workshop focuses on how new and existing wafer metrology technologies can be used, modified, or enhanced to measure and improve 3D interconnect processes.

  • International Symposium on Advanced Gate Stack Technology, Fall

This year's annual symposium, "Functional Stacks for Logic and Memory Devices," explores functional stacks for future (sub-22 nm node) devices, including high-k/metal gate stacks for Si, SiGe, and III-V high performance MOSFETs; metal/high-k/metal gate stacks for storage capacitors and resistive change memory; high-k/metal gate for flash memory; insulators and metals for high-performance NEMS and sensors; and magnetic material stacks for spin-based devices. The symposium will feature industry experts presenting their latest research in both invited and contributed talks and a discussion panel of representatives from major semiconductor device makers, equipment makers, and academia.

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