MoSys to Present on Technical Panel and Demonstrate Interoperability of its Bandwidth Engine® IC at DesignCon 2011

SANTA CLARA, Calif. — (BUSINESS WIRE) — February 1, 2011 — MoSys, Inc. (NASDAQ: MOSY):


MoSys (NASDAQ: MOSY), a leading architect of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, is participating at DesignCon 2011. Michael Miller, Vice President of Technology Innovation and System Applications at MoSys, is a panellist of the session titled, “ Meeting Chip to Chip I/O Demands of 100G and Beyond Line Cards” being held on Wednesday, February 2, 2011, at 3:30 – 4:30 p.m. Joining Miller for the MoSys sponsored panel are panellists from Avago Technologies, Cadence Design Systems and Xilinx, Inc. The panel will be introduced and moderated by Andrew Schmitt, Directing Analyst, Optical of Infonetics Research. Additionally, MoSys will be demonstrating the interoperability of its Bandwidth Engine® IC with SerDes from Avago and with FPGA devices from both Altera Corporation and Xilinx, Inc. at booth 516.

What: DesignCon 2011 is the must-attend event for chip level design engineers. It is the place for this community to network, identify solutions to immediate design challenges, and meet in person the solution providers for your next project. DesignCon brings together engineers, suppliers, analysts and media from across the globe. DesignCon’s exhibit floor offers the semiconductor and electronic design engineering communities a place to showcase their latest technologies and developments.
When: DesignCon 2011’s conference begins January 31, 2011 and concludes February 3, 2011. The two-day exhibition is February 1 – 2, 2011.
Where: Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054

About MoSys, Inc.

MoSys, Inc. (NASDAQ: MOSY) is a leading architect of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs. MoSys’ Bandwidth Engine™ family of ICs combines the company’s patented 1T-SRAM® high-density memory technology with its high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology. A key element of Bandwidth Engine technology is the GigaChip™ Interface, an open, CEI-11 compatible interface developed to enable highly efficient serial chip-to-chip communications. MoSys' IP portfolio includes SerDes IP and DDR3 PHYs that support data rates from 1 - 11 Gbps across a variety of standards. In addition, MoSys offers its flagship, patented 1T-SRAM and 1T-Flash <

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