ADVISORY/Real Intent Participates in Language Day Debate, Presents Technical Session, Invites Designers to Its Verification Test Drive Suite

  • (BUSINESS WIRE)--


    Language Debate Is Thursday, November 15; Technical Presentation on

    Verification Economics Is Wednesday, November 14

    Who:
    
    Dr. Prakash Narain, Real Intent's President and CEO will participate
    in a Language Day debate at EDA Front-to-Back (
    www.edafronttoback.com)
    and will present a session on verification economics.
    Designers and verification specialists are invited.
    
    
    What:
    
    The Great Language Debate
    
    Prakash Narain will participate on a panel moderated by Netronics'
    Editor-in-Chief, Tets Maniwa. The panel will debate two approaches to
    the design style of the future -- the existing HDL based approach on
    one side, and the C++ Language approach on the other. The primary
    question that the panel will attempt to answer is "Which style will
    dominate in five years?"
    
    Presentation
    
    Title: Rescuing Verification Economics with Formal Functional
    Verification
    
    Formal verification has always had the promise of being an effective
    verification approach as complement to simulation-based approaches.
    This session describes the benefits of formal verification and how
    today's design teams can implement and capitalize on this approach.
    
    
    When:
    
    Language Day Debate
    Thursday, November 15, 2001
    10:00 a.m.-12:00 p.m.
    
    Presentation
    Wednesday, November 14, 2001
    2:30 p.m.-3:30 p.m.
    
    Test Drives
    Wednesday, November 14, 2001, 10 a.m.-5 p.m.
    Thursday, November 15, 2001, 10 a.m.-3 p.m.
    To make a test drive appointment, contact Steve Pollock at
    408/982-5412 or 
    Email Contact
    
    
    Where:
    
    San Jose McEnery Convention Center
    408 Almaden Blvd.
    San Jose, CA 95110-2715
    

    About Real Intent:

    Real Intent, headquartered in San Jose, California, offers award winning formal functional verification tools for electronic design. These tools give users the capability to comprehensively verify designs early. These products significantly reduce the cost of verifying integrated circuits, electronic systems and system on a chip. For more information, email: Email Contact, web: http://www.realintent.com.

    Real Intent acknowledges trademarks or registered trademarks of other organizations for their respective products and services.


    Contact:
         ValleyPR for Real Intent
         Georgia Marszalek, 650/345-7477
         
    Email Contact



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