"Lattice Diamond" FPGA Design Software Heralds New Era for Low Power, Cost Sensitive FPGA Applications

HILLSBORO, OR -- (MARKET WIRE) -- Jun 28, 2010 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 1.0 of its Lattice Diamond™ FPGA design software, the new flagship design environment for Lattice FPGA products. Lattice Diamond software provides a complete set of powerful tools, efficient design flows and modern user interface that enables designers to more quickly target low power, cost sensitive FPGA applications.

Video demonstrations of the Lattice Diamond design software can be viewed here: www.latticesemi.com/latticediamond/videos

Photos of the Lattice Diamond design software can be viewed here: http://www.latticesemi.com/dmdImg.htm

"We have used Lattice Diamond design software at Helion for the development of the Ionos line of video image processing pipeline IP, and were very impressed by the level of integration of so many different and powerful software tools into one GUI," said Dr. Arndt Bussman, CTO of Helion GmbH. "This integration takes our FPGA code development process to unprecedented levels of design productivity and quality."

"Diamond software gives our customers an easy to use, intuitive design environment that specifically addresses the critical design issues of cost sensitive, lower power applications. As designs become larger, and FPGAs are increasingly being used in more cost sensitive, high volume applications, designers need an easy to learn, flexible design environment for exploring different implementations to achieve their cost, power, and performance targets," said Mike Kendrick, Lattice's Manager of Software Product Planning. "The Diamond software allows designers to efficiently manage these multiple implementations in one project. In addition, Diamond software continues to provide the industry-leading features previously released within our ispLEVER® design environment that are specifically developed for low cost and low power applications. These include a very accurate power calculator, simultaneous switching output noise calculator, and the proven MAP and PAR FPGA implementation algorithms that take novel approaches to avoid congestion when targeting Lattice's industry-leading FPGA product line."

Intuitive Modern User Interface for a New Generation of Design Tools
Diamond software enables designers to move quickly to the task at hand because navigation is direct and intuitive. Designers can manage their design view windows through the attach/detach feature. This feature allows the activation of many alternate concurrent design views across the available screen space, yet avoids the clutter that could result without advanced window management. Combined with the extensive cross-probing between Diamond Views, designers can quickly investigate their design implementation's utilization and critical timing.

Design Exploration Made Easy
Diamond software supports multiple design Implementations. The design source can be shared among Implementations, or each Implementation can have its own unique design source. This allows design exploration from within the Diamond software: different approaches can be tried to evaluate their effect on design size, cost, performance and power. Optimization options for logic synthesis and place and route are captured as a Strategy that can be applied easily to any of the Implementations. Diamond software comes with a library of pre-defined Strategies, and users can also create their own and add them to this library. A single Strategy's settings can be updated, for example to an alternate PAR algorithm tuned for highly connected designs, and run against several unique Implementations to determine if the results better meet the design goals for cost, power and performance. Finally, the Run Manager can launch a user-selected set of Implementations to be run through the flow, exploiting multi-core processors, if available, to improve the elapsed time to final results.

Improved Designer Productivity
The Diamond design environment includes many other design flow improvements that specifically improve designer productivity, particularly when targeting low power, cost sensitive applications. For example, built-in HDL visualization and code checking saves time by quickly catching coding errors and improving design documentation. As another example, designers can quickly find, investigate and address timing issues using the new Timing Analysis View. The Timing Analysis View allows easy navigation of the static timing results. When timing constraints are revised, direct updates to timing analysis avoid the potentially significant time required to re-implement the design. Diamond software also includes extensive capabilities for scripting the design flow. Tcl command dictionaries specific to the Diamond design environment are available for projects, netlists, HDL code checking, power calculation and hardware debug insertion and analysis.

Expanded Platform Support
The Diamond design environment is supported on Windows and Linux. It includes support for Windows 7, and under Windows 7 64-bit, Diamond software has access to a full 4G memory space. This allows designers targeting even the largest LatticeECP3™ devices unprecedented system performance and flexibility. The Diamond design environment includes support of Windows XP, Windows Vista (32 bit), and Windows 7 (32 bit and 64 bit), as well as Linux (Red Hat Enterprise Linux and Novell SUSE).

Other Lattice Design Software
Other Lattice design tools are available for download separately, including LatticeMico32™ System and ispLEVER Classic, as well as the PAC-Designer® tools that target programmable mixed signal design. A Lattice Diamond license will also enable any of those tools that are under license control.

Third Party Tool Support
Synopsys' Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec's Active-HDL Lattice Edition II simulator is included for Windows. In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 FPGA family.

Support for ispLEVER Design Software
Lattice will continue to support its ispLEVER tool suite for FPGA design over the next 18 months while transitioning its FPGA customer base to the Diamond design environment. There are no changes to the ispLEVER Classic product, which targets CPLD and legacy FPGA devices.

Pricing and Availability
The Lattice Diamond software is available now for download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either the Diamond free license or the Diamond subscription license. The Diamond free license can be immediately generated upon request from the Lattice website and provides access to many popular Lattice devices such as the MachXO™ PLD family, the LatticeXP2™ FPGA family and the LatticeECP2™ FPGA family at no cost. The Diamond free license also enables Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Web Edition II simulation software.

The Diamond subscription license that can be purchased adds support for all Lattice FPGAs, including the latest LatticeECP3 devices. It enables Synopsys Synplify Pro for Lattice synthesis and the Aldec Lattice Edition II mixed language simulator for increased capacity and performance. The Diamond subscription license enables both the new Diamond software and existing ispLEVER software from a single license. The Diamond subscription license price is $895 per year. All Lattice ispLEVER software users under active maintenance agreements will receive a Diamond subscription license for no charge that will expire one year from the Lattice Diamond 1.0 release date.

About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispLEVER, LatticeECP2, LatticeECP3, LatticeXP2, Lattice Diamond, LatticeMico32, MachXO, PAC-Designer and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Brian Kiernan
Corporate Communications Manager 
Lattice Semiconductor Corporation 
503-268-8739 voice
503-268-8193 fax

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